📄 buzz2.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: buzz2 Date: 11-19-2002, 8:17AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
26 /108 ( 24%) 33 /540 ( 6%) 17 /108 ( 15%) 18 /69 ( 26%) 34 /216 ( 15%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 8 8 | I/O : 17 46
Output : 9 9 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 17
Non-registered Macrocell driving I/O 9
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 26 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 26 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
buzzout 8 16 FB4_14 STD FAST 68 I/O O
counter_0 1 1 FB5_18 STD (b) (b)
counter_1 1 1 FB5_17 STD 44 I/O (b)
counter_10 1 10 FB4_18 STD (b) (b)
counter_11 1 11 FB4_17 STD 70 I/O (b)
counter_12 1 12 FB4_16 STD (b) (b)
counter_13 1 13 FB4_15 STD 69 I/O (b)
counter_14 1 14 FB4_13 STD (b) (b)
counter_15 1 15 FB4_12 STD 67 I/O (b)
counter_16 1 16 FB4_11 STD 66 I/O (b)
counter_2 1 2 FB4_10 STD (b) (b)
counter_3 1 3 FB4_9 STD 65 I/O (b)
counter_4 1 4 FB4_8 STD 63 I/O I
counter_5 1 5 FB4_7 STD (b) (b)
counter_6 1 6 FB4_6 STD 62 I/O I
counter_7 1 7 FB4_5 STD 61 I/O I
counter_8 1 8 FB4_4 STD (b) (b)
counter_9 1 9 FB4_3 STD 58 I/O I
ledout<0> 1 1 FB3_17 STD FAST 31 I/O O
ledout<1> 1 1 FB5_2 STD FAST 32 I/O O
ledout<2> 1 1 FB5_3 STD FAST 33 I/O O
ledout<3> 1 1 FB5_5 STD FAST 34 I/O O
ledout<4> 1 1 FB5_6 STD FAST 35 I/O O
ledout<5> 1 1 FB5_8 STD FAST 36 I/O O
ledout<6> 1 1 FB5_9 STD FAST 37 I/O O
ledout<7> 1 1 FB5_11 STD FAST 39 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_12 9 GCK/I/O GCK
keyin<0> FB6_14 54 I/O I
keyin<1> FB6_15 55 I/O I
keyin<2> FB6_17 56 I/O I
keyin<3> FB4_2 57 I/O I
keyin<4> FB4_3 58 I/O I
keyin<5> FB4_5 61 I/O I
keyin<6> FB4_6 62 I/O I
keyin<7> FB4_8 63 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 12
FB2 0 0 0 0 0/0 12
FB3 1 1 1 1 1/0 12
FB4 16 25 25 23 1/0 11
FB5 9 8 8 9 7/0 11
FB6 0 0 0 0 0/0 11
---- ----- ----- -----
26 33 9/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 7 I/O
(unused) 0 0 0 5 FB1_12 9 GCK/I/O GCK
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 10 GCK/I/O
(unused) 0 0 0 5 FB1_15 11 I/O
(unused) 0 0 0 5 FB1_16 12 GCK/I/O
(unused) 0 0 0 5 FB1_17 13 I/O
(unused) 0 0 0 5 FB1_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
(unused) 0 0 0 5 FB2_3 72 I/O
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 74 GSR/I/O
(unused) 0 0 0 5 FB2_6 75 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 76 GTS/I/O
(unused) 0 0 0 5 FB2_9 77 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 79 I/O
(unused) 0 0 0 5 FB2_12 80 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 82 I/O
(unused) 0 0 0 5 FB2_16 83 I/O
(unused) 0 0 0 5 FB2_17 84 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 1/35
Number of signals used by logic mapping into function block: 1
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 14 I/O
(unused) 0 0 0 5 FB3_3 15 I/O
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 17 I/O
(unused) 0 0 0 5 FB3_6 18 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 19 I/O
(unused) 0 0 0 5 FB3_9 20 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 21 I/O
(unused) 0 0 0 5 FB3_12 23 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 24 I/O
(unused) 0 0 0 5 FB3_15 25 I/O
(unused) 0 0 0 5 FB3_16 26 I/O
ledout<0> 1 0 0 4 FB3_17 STD 31 I/O O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: "keyin<0>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
ledout<0> X....................................... 1 1
0----+----1----+----2----+----3----+----4
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