buzz1.rpt

利用xilinx实现一个简易的电子琴。简谱中的音名与频率一一对应。

  7: "$OpTx$N1454/N1454_D2_INV$1302" 
                       18: "N229/N229_D.FBK".LFBK 
                                             28: counter_6.FBK.LFBK 
  8: "$OpTx$N1531/N1531_D2_INV$1303" 
                       19: "N230/N230_D.FBK".LFBK 
                                             29: counter_7.FBK.LFBK 
  9: "$OpTx$N1602/N1602_D2_INV$1304" 
                       20: "N231/N231_D.FBK".LFBK 
                                             30: counter_8.FBK.LFBK 
 10: "$OpTx$N1670/N1670_D2_INV$1305" 
                       21: "N232/N232_D.FBK".LFBK 
                                             31: counter_9.FBK.LFBK 
 11: "$OpTx$N452/N452_D2_INV$1306" 
                      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
counter_9            XXXXXXXXXXXXXXXX....X................... 17      17
counter_8            XXXXXXXXXXXXXXXX...X.................... 17      17
counter_7            XXXXXXXXXXXXXXXX..X..................... 17      17
counter_6            XXXXXXXXXXXXXXXX.X...................... 17      17
counter_5            XXXXXXXXXXXXXXXXX....................... 17      17
N232/N232_D          .....................XXXXXXXXXX......... 10      10
N231/N231_D          .....................XXXXXXXXX.......... 9       9
N230/N230_D          .....................XXXXXXXX........... 8       8
N229/N229_D          .....................XXXXXXX............ 7       7
N228/N228_D          .....................XXXXXX............. 6       6
N227/N227_D          .....................XXXXX.............. 5       5
N226/N226_D          .....................XXXX............... 4       4
N225/N225_D          .....................XXX................ 3       3
N224/N224_D          .....................XX................. 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               28/8
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         14    I/O     
N223/N223_D           2       0     0   3     FB3_3   STD   15    I/O     (b)
N222/N222_D           2       0     0   3     FB3_4   STD         (b)     (b)
N221/N221_D           2       0     0   3     FB3_5   STD   17    I/O     (b)
N220/N220_D           2       0     0   3     FB3_6   STD   18    I/O     (b)
N219/N219_D           2       0     0   3     FB3_7   STD         (b)     (b)
N218/N218_D           2       0     0   3     FB3_8   STD   19    I/O     (b)
N217/N217_D           2       0     0   3     FB3_9   STD   20    I/O     (b)
N216/N216_D           2       0     0   3     FB3_10  STD         (b)     (b)
N215/N215_D           2       0     0   3     FB3_11  STD   21    I/O     (b)
N1837/N1837_D2        4       0     0   1     FB3_12  STD   23    I/O     (b)
$OpTx$N1531/N1531_D2_INV$1303
                      4       0     0   1     FB3_13  STD         (b)     (b)
$OpTx$N1454/N1454_D2_INV$1302
                      4       0     0   1     FB3_14  STD   24    I/O     (b)
$OpTx$N1162/N1162_D2_INV$1298
                      4       0     0   1     FB3_15  STD   25    I/O     (b)
N1831/N1831_D2        5       0     0   0     FB3_16  STD   26    I/O     (b)
ledout<0>             1       0     0   4     FB3_17  STD   31    I/O     O
$OpTx$N1238/N1238_D2_INV$1299
                      5       0     0   0     FB3_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "keyin<0>"        11: counter_10        20: counter_19 
  2: "keyin<1>"        12: counter_11        21: counter_2 
  3: "keyin<2>"        13: counter_12        22: counter_3 
  4: "keyin<3>"        14: counter_13        23: counter_4 
  5: "keyin<4>"        15: counter_14        24: counter_5 
  6: "keyin<5>"        16: counter_15        25: counter_6 
  7: "keyin<6>"        17: counter_16        26: counter_7 
  8: "keyin<7>"        18: counter_17        27: counter_8 
  9: counter_0         19: counter_18        28: counter_9 
 10: counter_1        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
N223/N223_D          ........XXXXXXXXXXXXXXXXXXXX............ 20      20
N222/N222_D          ........XXXXXXXXXXX.XXXXXXXX............ 19      19
N221/N221_D          ........XXXXXXXXXX..XXXXXXXX............ 18      18
N220/N220_D          ........XXXXXXXXX...XXXXXXXX............ 17      17
N219/N219_D          ........XXXXXXXX....XXXXXXXX............ 16      16
N218/N218_D          ........XXXXXXX.....XXXXXXXX............ 15      15
N217/N217_D          ........XXXXXX......XXXXXXXX............ 14      14
N216/N216_D          ........XXXXX.......XXXXXXXX............ 13      13
N215/N215_D          ........XXXX........XXXXXXXX............ 12      12
N1837/N1837_D2       XXXXXXXX................................ 8       8
$OpTx$N1531/N1531_D2_INV$1303 
                     XXXXXXXX................................ 8       8
$OpTx$N1454/N1454_D2_INV$1302 
                     XXXXXXXX................................ 8       8
$OpTx$N1162/N1162_D2_INV$1298 
                     XXXXXXXX................................ 8       8
N1831/N1831_D2       XXXXXXXX................................ 8       8
ledout<0>            X....................................... 1       1
$OpTx$N1238/N1238_D2_INV$1299 
                     XXXXXXXX................................ 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
(unused)              0       0     0   5     FB4_2         57    I/O     I
counter_4             2       0     0   3     FB4_3   STD   58    I/O     I
counter_3             2       0     0   3     FB4_4   STD         (b)     (b)
counter_2             2       0     0   3     FB4_5   STD   61    I/O     I
counter_19            2       0     0   3     FB4_6   STD   62    I/O     I
counter_18            2       0     0   3     FB4_7   STD         (b)     (b)
counter_17            2       0     0   3     FB4_8   STD   63    I/O     I
counter_16            2       0     0   3     FB4_9   STD   65    I/O     (b)
counter_15            2       0     0   3     FB4_10  STD         (b)     (b)
counter_14            2       0     0   3     FB4_11  STD   66    I/O     (b)
counter_13            2       0     0   3     FB4_12  STD   67    I/O     (b)
counter_12            2       0     0   3     FB4_13  STD         (b)     (b)
buzzout               2       0     0   3     FB4_14  STD   68    I/O     O
counter_11            2       0     0   3     FB4_15  STD   69    I/O     (b)
counter_10            2       0     0   3     FB4_16  STD         (b)     (b)
counter_1             2       0     0   3     FB4_17  STD   70    I/O     (b)
counter_0             2       0     0   3     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "$OpTx$FX_DC$1145" 
                       12: "$OpTx$N916/N916_D2_INV$1307" 
                                             22: "N219/N219_D" 
  2: "$OpTx$N1053/N1053_D2_INV$1297" 
                       13: "N1814/N1814_D2"  23: "N220/N220_D" 
  3: "$OpTx$N1162/N1162_D2_INV$1298" 
                       14: "N1822/N1822_D2"  24: "N221/N221_D" 
  4: "$OpTx$N1238/N1238_D2_INV$1299" 
                       15: "N1831/N1831_D2"  25: "N222/N222_D" 
  5: "$OpTx$N1308/N1308_D2_INV$1300" 
                       16: "N1837/N1837_D2"  26: "N223/N223_D" 
  6: "$OpTx$N1378/N1378_D2_INV$1301" 
                       17: "N214/N214_D"     27: "N224/N224_D" 
  7: "$OpTx$N1454/N1454_D2_INV$1302" 
                       18: "N215/N215_D"     28: "N225/N225_D" 
  8: "$OpTx$N1531/N1531_D2_INV$1303" 
                       19: "N216/N216_D"     29: "N226/N226_D" 
  9: "$OpTx$N1602/N1602_D2_INV$1304" 
                       20: "N217/N217_D"     30: "N227/N227_D" 
 10: "$OpTx$N1670/N1670_D2_INV$1305" 
                       21: "N218/N218_D"     31: counter_0.FBK.LFBK 
 11: "$OpTx$N452/N452_D2_INV$1306" 
                      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
counter_4            XXXXXXXXXXXXXXXX.............X.......... 17      17
counter_3            XXXXXXXXXXXXXXXX............X........... 17      17
counter_2            XXXXXXXXXXXXXXXX...........X............ 17      17
counter_19           XXXXXXXXXXXXXXXX.........X.............. 17      17
counter_18           XXXXXXXXXXXXXXXX........X............... 17      17
counter_17           XXXXXXXXXXXXXXXX.......X................ 17      17
counter_16           XXXXXXXXXXXXXXXX......X................. 17      17
counter_15           XXXXXXXXXXXXXXXX.....X.................. 17      17
counter_14           XXXXXXXXXXXXXXXX....X................... 17      17
counter_13           XXXXXXXXXXXXXXXX...X.................... 17      17
counter_12           XXXXXXXXXXXXXXXX..X..................... 17      17
buzzout              XXXXXXXXXXXXXXXX........................ 16      16
counter_11           XXXXXXXXXXXXXXXX.X...................... 17      17
counter_10           XXXXXXXXXXXXXXXXX....................... 17      17
counter_1            XXXXXXXXXXXXXXXX..........X............. 17      17
counter_0            XXXXXXXXXXXXXXXX..............X......... 17      17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining:               8/28
Number of signals used by logic mapping into function block:  8
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
$OpTx$N452/N452_D2_INV$1306
                      8       4<- /\1   0     FB5_1   STD         (b)     (b)
ledout<1>             1       0   /\4   0     FB5_2   STD   32    I/O     O
ledout<2>             1       0     0   4     FB5_3   STD   33    I/O     O
(unused)              0       0     0   5     FB5_4               (b)     
ledout<3>             1       0     0   4     FB5_5   STD   34    I/O     O
ledout<4>             1       0   \/1   3     FB5_6   STD   35    I/O     O
N1822/N1822_D2        6       1<-   0   0     FB5_7   STD         (b)     (b)
ledout<5>             1       0     0   4     FB5_8   STD   36    I/O     O
ledout<6>             1       0   \/1   3     FB5_9   STD   37    I/O     O
$OpTx$N1602/N1602_D2_INV$1304
                      6       1<-   0   0     FB5_10  STD         (b)     (b)
ledout<7>             1       0   \/3   1     FB5_11  STD   39    I/O     O
$OpTx$N1378/N1378_D2_INV$1301
                      6       3<- \/2   0     FB5_12  STD   40    I/O     (b)
$OpTx$N1308/N1308_D2_INV$1300
                      6       2<- \/1   0     FB5_13  STD         (b)     (b)
$OpTx$N1053/N1053_D2_INV$1297
                      6       1<-   0   0     FB5_14  STD   41    I/O     (b)
(unused)              0       0   \/5   0     FB5_15        43    I/O     (b)
N1814/N1814_D2        7       5<- \/3   0     FB5_16  STD         (b)     (b)
$OpTx$N916/N916_D2_INV$1307
                      7       3<- \/1   0     FB5_17  STD   44    I/O     (b)
$OpTx$N1670/N1670_D2_INV$1305
                      7       2<-   0   0     FB5_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "keyin<0>"         4: "keyin<3>"         7: "keyin<6>" 
  2: "keyin<1>"         5: "keyin<4>"         8: "keyin<7>" 
  3: "keyin<2>"         6: "keyin<5>"       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
$OpTx$N452/N452_D2_INV$1306 
                     XXXXXXXX................................ 8       8