📄 buzz1.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: buzz1 Date: 11-19-2002, 8:47AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
64 /108 ( 59%) 213 /540 ( 39%) 21 /108 ( 19%) 18 /69 ( 26%) 144/216 ( 66%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 8 8 | I/O : 17 46
Output : 9 9 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 21
Non-registered Macrocell driving I/O 8
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 64 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 64 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
$OpTx$FX_DC$1145 40 35 FB1_15 STD 11 I/O (b)
$OpTx$N1053/N1053_D2_INV$1297 6 8 FB5_14 STD 41 I/O (b)
$OpTx$N1162/N1162_D2_INV$1298 4 8 FB3_15 STD 25 I/O (b)
$OpTx$N1238/N1238_D2_INV$1299 5 8 FB3_18 STD (b) (b)
$OpTx$N1308/N1308_D2_INV$1300 6 8 FB5_13 STD (b) (b)
$OpTx$N1378/N1378_D2_INV$1301 6 8 FB5_12 STD 40 I/O (b)
$OpTx$N1454/N1454_D2_INV$1302 4 8 FB3_14 STD 24 I/O (b)
$OpTx$N1531/N1531_D2_INV$1303 4 8 FB3_13 STD (b) (b)
$OpTx$N1602/N1602_D2_INV$1304 6 8 FB5_10 STD (b) (b)
$OpTx$N1670/N1670_D2_INV$1305 7 8 FB5_18 STD (b) (b)
$OpTx$N452/N452_D2_INV$1306 8 8 FB5_1 STD (b) (b)
$OpTx$N916/N916_D2_INV$1307 7 8 FB5_17 STD 44 I/O (b)
N1814/N1814_D2 7 8 FB5_16 STD (b) (b)
N1822/N1822_D2 6 8 FB5_7 STD (b) (b)
N1831/N1831_D2 5 8 FB3_16 STD 26 I/O (b)
N1837/N1837_D2 4 8 FB3_12 STD 23 I/O (b)
N214/N214_D 2 11 FB6_18 STD (b) (b)
N215/N215_D 2 12 FB3_11 STD 21 I/O (b)
N216/N216_D 2 13 FB3_10 STD (b) (b)
N217/N217_D 2 14 FB3_9 STD 20 I/O (b)
N218/N218_D 2 15 FB3_8 STD 19 I/O (b)
N219/N219_D 2 16 FB3_7 STD (b) (b)
N220/N220_D 2 17 FB3_6 STD 18 I/O (b)
N221/N221_D 2 18 FB3_5 STD 17 I/O (b)
N222/N222_D 2 19 FB3_4 STD (b) (b)
N223/N223_D 2 20 FB3_3 STD 15 I/O (b)
N224/N224_D 2 2 FB2_18 STD (b) (b)
N225/N225_D 2 3 FB2_17 STD 84 I/O (b)
N226/N226_D 2 4 FB2_16 STD 83 I/O (b)
N227/N227_D 2 5 FB2_15 STD 82 I/O (b)
N228/N228_D 2 6 FB2_14 STD 81 I/O (b)
N229/N229_D 2 7 FB2_13 STD (b) (b)
N230/N230_D 2 8 FB2_12 STD 80 I/O (b)
N231/N231_D 2 9 FB2_11 STD 79 I/O (b)
N232/N232_D 2 10 FB2_10 STD (b) (b)
buzzout 2 16 FB4_14 STD FAST 68 I/O O
counter_0 2 17 FB4_18 STD (b) (b)
counter_1 2 17 FB4_17 STD 70 I/O (b)
counter_10 2 17 FB4_16 STD (b) (b)
counter_11 2 17 FB4_15 STD 69 I/O (b)
counter_12 2 17 FB4_13 STD (b) (b)
counter_13 2 17 FB4_12 STD 67 I/O (b)
counter_14 2 17 FB4_11 STD 66 I/O (b)
counter_15 2 17 FB4_10 STD (b) (b)
counter_16 2 17 FB4_9 STD 65 I/O (b)
counter_17 2 17 FB4_8 STD 63 I/O I
counter_18 2 17 FB4_7 STD (b) (b)
counter_19 2 17 FB4_6 STD 62 I/O I
counter_2 2 17 FB4_5 STD 61 I/O I
counter_3 2 17 FB4_4 STD (b) (b)
counter_4 2 17 FB4_3 STD 58 I/O I
counter_5 2 17 FB2_9 STD 77 GTS/I/O (b)
counter_6 2 17 FB2_8 STD 76 GTS/I/O (b)
counter_7 2 17 FB2_7 STD (b) (b)
counter_8 2 17 FB2_6 STD 75 I/O (b)
counter_9 2 17 FB2_5 STD 74 GSR/I/O (b)
ledout<0> 1 1 FB3_17 STD FAST 31 I/O O
ledout<1> 1 1 FB5_2 STD FAST 32 I/O O
ledout<2> 1 1 FB5_3 STD FAST 33 I/O O
ledout<3> 1 1 FB5_5 STD FAST 34 I/O O
ledout<4> 1 1 FB5_6 STD FAST 35 I/O O
ledout<5> 1 1 FB5_8 STD FAST 36 I/O O
ledout<6> 1 1 FB5_9 STD FAST 37 I/O O
ledout<7> 1 1 FB5_11 STD FAST 39 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_12 9 GCK/I/O GCK
keyin<0> FB6_14 54 I/O I
keyin<1> FB6_15 55 I/O I
keyin<2> FB6_17 56 I/O I
keyin<3> FB4_2 57 I/O I
keyin<4> FB4_3 58 I/O I
keyin<5> FB4_5 61 I/O I
keyin<6> FB4_6 62 I/O I
keyin<7> FB4_8 63 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 1 35 35 40 0/0 12
FB2 14 31 31 28 0/0 12
FB3 16 28 28 45 1/0 12
FB4 16 31 31 32 1/0 11
FB5 16 8 8 66 7/0 11
FB6 1 11 11 2 0/0 11
---- ----- ----- -----
64 213 9/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 \/5 0 FB1_11 7 I/O (b)
(unused) 0 0 \/5 0 FB1_12 9 GCK/I/O GCK
(unused) 0 0 \/5 0 FB1_13 (b) (b)
(unused) 0 0 \/5 0 FB1_14 10 GCK/I/O (b)
$OpTx$FX_DC$1145 40 35<- 0 0 FB1_15 STD 11 I/O (b)
(unused) 0 0 /\5 0 FB1_16 12 GCK/I/O (b)
(unused) 0 0 /\5 0 FB1_17 13 I/O (b)
(unused) 0 0 /\5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$N1053/N1053_D2_INV$1297"
13: "N1822/N1822_D2" 25: "N223/N223_D"
2: "$OpTx$N1162/N1162_D2_INV$1298"
14: "N1831/N1831_D2" 26: "N224/N224_D"
3: "$OpTx$N1238/N1238_D2_INV$1299"
15: "N1837/N1837_D2" 27: "N225/N225_D"
4: "$OpTx$N1308/N1308_D2_INV$1300"
16: "N214/N214_D" 28: "N226/N226_D"
5: "$OpTx$N1378/N1378_D2_INV$1301"
17: "N215/N215_D" 29: "N227/N227_D"
6: "$OpTx$N1454/N1454_D2_INV$1302"
18: "N216/N216_D" 30: "N228/N228_D"
7: "$OpTx$N1531/N1531_D2_INV$1303"
19: "N217/N217_D" 31: "N229/N229_D"
8: "$OpTx$N1602/N1602_D2_INV$1304"
20: "N218/N218_D" 32: "N230/N230_D"
9: "$OpTx$N1670/N1670_D2_INV$1305"
21: "N219/N219_D" 33: "N231/N231_D"
10: "$OpTx$N452/N452_D2_INV$1306"
22: "N220/N220_D" 34: "N232/N232_D"
11: "$OpTx$N916/N916_D2_INV$1307"
23: "N221/N221_D" 35: counter_0
12: "N1814/N1814_D2" 24: "N222/N222_D"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
$OpTx$FX_DC$1145 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX..... 35 35
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
(unused) 0 0 0 5 FB2_3 72 I/O
(unused) 0 0 0 5 FB2_4 (b)
counter_9 2 0 0 3 FB2_5 STD 74 GSR/I/O (b)
counter_8 2 0 0 3 FB2_6 STD 75 I/O (b)
counter_7 2 0 0 3 FB2_7 STD (b) (b)
counter_6 2 0 0 3 FB2_8 STD 76 GTS/I/O (b)
counter_5 2 0 0 3 FB2_9 STD 77 GTS/I/O (b)
N232/N232_D 2 0 0 3 FB2_10 STD (b) (b)
N231/N231_D 2 0 0 3 FB2_11 STD 79 I/O (b)
N230/N230_D 2 0 0 3 FB2_12 STD 80 I/O (b)
N229/N229_D 2 0 0 3 FB2_13 STD (b) (b)
N228/N228_D 2 0 0 3 FB2_14 STD 81 I/O (b)
N227/N227_D 2 0 0 3 FB2_15 STD 82 I/O (b)
N226/N226_D 2 0 0 3 FB2_16 STD 83 I/O (b)
N225/N225_D 2 0 0 3 FB2_17 STD 84 I/O (b)
N224/N224_D 2 0 0 3 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$1145"
12: "$OpTx$N916/N916_D2_INV$1307"
22: counter_0
2: "$OpTx$N1053/N1053_D2_INV$1297"
13: "N1814/N1814_D2" 23: counter_1
3: "$OpTx$N1162/N1162_D2_INV$1298"
14: "N1822/N1822_D2" 24: counter_2
4: "$OpTx$N1238/N1238_D2_INV$1299"
15: "N1831/N1831_D2" 25: counter_3
5: "$OpTx$N1308/N1308_D2_INV$1300"
16: "N1837/N1837_D2" 26: counter_4
6: "$OpTx$N1378/N1378_D2_INV$1301"
17: "N228/N228_D.FBK".LFBK
27: counter_5.FBK.LFBK
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