buzz1.syr

利用xilinx实现一个简易的电子琴。简谱中的音名与频率一一对应。

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : buzz1.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : buzz1
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : buzz1
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : buzz1.prj
Compiling included source file 'buzz1.v'
Module <buzz1> compiled.
Continuing compilation of source file 'buzz1.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'buzz1.prj'
No errors in compilation
Analysis of file <buzz1.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <buzz1>.
Module <buzz1> is correct for synthesis.

Synthesizing Unit <buzz1>.
    Related source file is buzz1.v.
    Found 20-bit comparator equal for signal <$n0017> created at line 13.
    Found 20-bit adder for signal <$old_counter_1>.
    Found 1-bit register for signal <buzzout_reg>.
    Found 20-bit register for signal <counter>.
    Summary:
	inferred  21 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <buzz1> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
  20-bit register                  : 1
  1-bit register                   : 1
# Adders/Subtractors               : 1
  20-bit adder                     : 1
# Comparators                      : 1
  20-bit comparator equal          : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <buzz1> ...
=========================================================================
Final Results
Output File Name                   : buzz1
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 39
  1-bit xor2                       : 39

Design Statistics
# Edif Instances                   : 390
# I/Os                             : 18

=========================================================================
CPU : 4.07 / 4.23 s | Elapsed : 5.00 / 5.00 s
 
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