pwm1.v

来自「xilinx设计并完成一个10位的D/F转换器」· Verilog 代码 · 共 36 行

module pwm(clock,keyin,pwm_out);
    input clock;
    input [1:0] keyin;
    output pwm_out;

  	 reg [15:0] count,count1;
	 reg [9:0] pwm_count;
	 reg pwm_reg;

always @(posedge clock)
begin
	count=count+1;
	count1=count1+1;
	if (count[15:6] == pwm_count)
		begin
		count=0;
		pwm_reg=~pwm_reg;
		end
end

always @(posedge count1[15])
begin
	if (!keyin[0])
	begin
			pwm_count=pwm_count+1;
	end
	else if (!keyin[1])
	begin
			pwm_count=pwm_count-1;
	end
end

assign pwm_out=pwm_reg;

endmodule