📄 pwm.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: pwm Date: 11-18-2002, 5:40PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
62 /108 ( 57%) 409 /540 ( 75%) 43 /108 ( 39%) 4 /69 ( 5%) 200/216 ( 92%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 3 60
Output : 1 1 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 4 4
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 43
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 62 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 62 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
$OpTx$$OpTx$FX_DC$18_INV$118 2 3 FB6_16 STD (b) (b)
$OpTx$FX_DC$19 2 4 FB6_15 STD 55 I/O I
$OpTx$FX_DC$20 2 5 FB6_14 STD 54 I/O I
$OpTx$FX_DC$21 2 6 FB6_13 STD (b) (b)
N243/N243_D 2 11 FB6_12 STD 53 I/O (b)
N244/N244_D 2 12 FB5_4 STD (b) (b)
N245/N245_D 2 13 FB5_3 STD 33 I/O (b)
N246/N246_D 2 14 FB5_15 STD 43 I/O (b)
N247/N247_D 2 15 FB5_2 STD 32 I/O (b)
N248/N248_D 2 16 FB5_16 STD (b) (b)
N249/N249_D 2 7 FB6_11 STD 52 I/O (b)
N250/N250_D 2 8 FB2_14 STD 81 I/O (b)
N251/N251_D 2 9 FB6_10 STD (b) (b)
N252/N252_D 2 10 FB6_9 STD 51 I/O (b)
N365/N365_D2 20 20 FB3_3 STD 15 I/O (b)
N428/N428_D2 1 3 FB6_6 STD 48 I/O (b)
N431/N431_D2 1 4 FB6_5 STD 47 I/O (b)
N434/N434_D2 1 5 FB6_4 STD (b) (b)
N437/N437_D2 1 6 FB6_3 STD 46 I/O (b)
count1_0 1 1 FB1_11 STD 7 I/O (b)
count1_1 1 1 FB1_10 STD (b) (b)
count1_10 1 10 FB3_18 STD (b) (b)
count1_11 1 11 FB3_11 STD 21 I/O (b)
count1_12 1 12 FB3_10 STD (b) (b)
count1_13 1 13 FB3_9 STD 20 I/O (b)
count1_14 1 14 FB3_8 STD 19 I/O (b)
count1_15 1 15 FB3_7 STD (b) (b)
count1_2 1 2 FB1_9 STD 6 I/O (b)
count1_3 1 3 FB1_8 STD 5 I/O (b)
count1_4 1 4 FB1_7 STD (b) (b)
count1_5 1 5 FB1_6 STD 4 I/O (b)
count1_6 1 6 FB1_5 STD 3 I/O (b)
count1_7 1 7 FB1_4 STD (b) (b)
count1_8 1 8 FB3_6 STD 18 I/O (b)
count1_9 1 9 FB3_5 STD 17 I/O (b)
count_0 20 21 FB2_17 STD 84 I/O (b)
count_1 2 3 FB6_8 STD 50 I/O (b)
count_10 19 20 FB1_13 STD (b) (b)
count_11 19 20 FB2_2 STD 71 I/O (b)
count_12 19 20 FB2_12 STD 80 I/O (b)
count_13 19 20 FB3_13 STD (b) (b)
count_14 19 20 FB3_16 STD 26 I/O (b)
count_15 19 20 FB5_18 STD (b) (b)
count_2 20 22 FB4_2 STD 57 I/O (b)
count_3 20 22 FB4_8 STD 63 I/O (b)
count_4 20 22 FB1_3 STD 2 I/O (b)
count_5 20 22 FB1_17 STD 13 I/O (b)
count_6 19 20 FB5_13 STD (b) (b)
count_7 19 20 FB5_11 STD 39 I/O (b)
count_8 19 20 FB5_6 STD 35 I/O (b)
count_9 19 20 FB6_1 STD (b) (b)
pwm_count_0 2 3 FB6_7 STD (b) (b)
pwm_count_1 3 4 FB6_17 STD 56 I/O (b)
pwm_count_2 3 5 FB4_6 STD 62 I/O (b)
pwm_count_3 3 6 FB4_10 STD (b) (b)
pwm_count_4 3 7 FB4_11 STD 66 I/O (b)
pwm_count_5 3 8 FB4_12 STD 67 I/O (b)
pwm_count_6 3 9 FB4_16 STD (b) (b)
pwm_count_7 3 10 FB4_17 STD 70 I/O (b)
pwm_count_8 3 11 FB4_18 STD (b) (b)
pwm_count_9 3 12 FB4_4 STD (b) (b)
pwm_out 20 20 FB4_14 STD FAST 68 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clock FB1_12 9 GCK/I/O GCK
keyin<0> FB6_14 54 I/O I
keyin<1> FB6_15 55 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 11 31 31 67 0/0 12
FB2 4 36 36 60 0/0 12
FB3 11 35 35 66 0/0 12
FB4 11 27 27 84 1/0 11
FB5 9 36 36 86 0/0 11
FB6 16 35 35 46 0/0 11
---- ----- ----- -----
62 409 1/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB1_1 (b) (b)
(unused) 0 0 \/5 0 FB1_2 1 I/O (b)
count_4 20 15<- 0 0 FB1_3 STD 2 I/O (b)
count1_7 1 1<- /\5 0 FB1_4 STD (b) (b)
count1_6 1 0 /\1 3 FB1_5 STD 3 I/O (b)
count1_5 1 0 0 4 FB1_6 STD 4 I/O (b)
count1_4 1 0 0 4 FB1_7 STD (b) (b)
count1_3 1 0 0 4 FB1_8 STD 5 I/O (b)
count1_2 1 0 0 4 FB1_9 STD 6 I/O (b)
count1_1 1 0 0 4 FB1_10 STD (b) (b)
count1_0 1 0 \/4 0 FB1_11 STD 7 I/O (b)
(unused) 0 0 \/5 0 FB1_12 9 GCK/I/O GCK
count_10 19 14<- 0 0 FB1_13 STD (b) (b)
(unused) 0 0 /\5 0 FB1_14 10 GCK/I/O (b)
(unused) 0 0 \/5 0 FB1_15 11 I/O (b)
(unused) 0 0 \/5 0 FB1_16 12 GCK/I/O (b)
count_5 20 15<- 0 0 FB1_17 STD 13 I/O (b)
(unused) 0 0 /\5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$20" 12: "N252/N252_D" 22: pwm_count_0
2: "$OpTx$FX_DC$21" 13: "N434/N434_D2" 23: pwm_count_1
3: "N243/N243_D" 14: "N437/N437_D2" 24: pwm_count_2
4: "N244/N244_D" 15: count1_0.FBK.LFBK 25: pwm_count_3
5: "N245/N245_D" 16: count1_1.FBK.LFBK 26: pwm_count_4
6: "N246/N246_D" 17: count1_2.FBK.LFBK 27: pwm_count_5
7: "N247/N247_D" 18: count1_3.FBK.LFBK 28: pwm_count_6
8: "N248/N248_D" 19: count1_4.FBK.LFBK 29: pwm_count_7
9: "N249/N249_D" 20: count1_5.FBK.LFBK 30: pwm_count_8
10: "N250/N250_D" 21: count1_6.FBK.LFBK 31: pwm_count_9
11: "N251/N251_D"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_4 X.XXXXXXXXXXX........XXXXXXXXXX......... 22 22
count1_7 ..............XXXXXXX................... 7 7
count1_6 ..............XXXXXX.................... 6 6
count1_5 ..............XXXXX..................... 5 5
count1_4 ..............XXXX...................... 4 4
count1_3 ..............XXX....................... 3 3
count1_2 ..............XX........................ 2 2
count1_1 ..............X......................... 1 1
count1_0 ..............X......................... 1 1
count_10 ..XXXXXXXXXX.........XXXXXXXXXX......... 20 20
count_5 .XXXXXXXXXXX.X.......XXXXXXXXXX......... 22 22
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB2_1 (b) (b)
count_11 19 14<- 0 0 FB2_2 STD 71 I/O (b)
(unused) 0 0 /\5 0 FB2_3 72 I/O (b)
(unused) 0 0 /\4 1 FB2_4 (b) (b)
(unused) 0 0 0 5 FB2_5 74 GSR/I/O
(unused) 0 0 0 5 FB2_6 75 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 76 GTS/I/O
(unused) 0 0 0 5 FB2_9 77 GTS/I/O
(unused) 0 0 \/1 4 FB2_10 (b) (b)
(unused) 0 0 \/5 0 FB2_11 79 I/O (b)
count_12 19 14<- 0 0 FB2_12 STD 80 I/O (b)
(unused) 0 0 /\5 0 FB2_13 (b) (b)
N250/N250_D 2 0 /\3 0 FB2_14 STD 81 I/O (b)
(unused) 0 0 \/5 0 FB2_15 82 I/O (b)
(unused) 0 0 \/5 0 FB2_16 83 I/O (b)
count_0 20 15<- 0 0 FB2_17 STD 84 I/O (b)
(unused) 0 0 /\5 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: "N243/N243_D" 13: count_10 25: count_8
2: "N244/N244_D" 14: count_11.FBK.LFBK 26: count_9
3: "N245/N245_D" 15: count_12.FBK.LFBK 27: pwm_count_0
4: "N246/N246_D" 16: count_13 28: pwm_count_1
5: "N247/N247_D" 17: count_14 29: pwm_count_2
6: "N248/N248_D" 18: count_15 30: pwm_count_3
7: "N249/N249_D" 19: count_2 31: pwm_count_4
8: "N250/N250_D.FBK".LFBK
20: count_3 32: pwm_count_5
9: "N251/N251_D" 21: count_4 33: pwm_count_6
10: "N252/N252_D" 22: count_5 34: pwm_count_7
11: count_0.FBK.LFBK 23: count_6 35: pwm_count_8
12: count_1 24: count_7 36: pwm_count_9
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_11 XXXXXXXXXX................XXXXXXXXXX.... 20 20
count_12 XXXXXXXXXX................XXXXXXXXXX.... 20 20
N250/N250_D ..........XX......XXXXXX................ 8 8
count_0 ..........X.XXXXXX....XXXXXXXXXXXXXX.... 21 21
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB3_1 (b) (b)
(unused) 0 0 \/5 0 FB3_2 14 I/O (b)
N365/N365_D2 20 15<- 0 0 FB3_3 STD 15 I/O (b)
(unused) 0 0 /\5 0 FB3_4 (b) (b)
count1_9 1 0 0 4 FB3_5 STD 17 I/O (b)
count1_8 1 0 0 4 FB3_6 STD 18 I/O (b)
count1_15 1 0 0 4 FB3_7 STD (b) (b)
count1_14 1 0 0 4 FB3_8 STD 19 I/O (b)
count1_13 1 0 0 4 FB3_9 STD 20 I/O (b)
count1_12 1 0 0 4 FB3_10 STD (b) (b)
count1_11 1 0 \/4 0 FB3_11 STD 21 I/O (b)
(unused) 0 0 \/5 0 FB3_12 23 I/O (b)
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