📄 fosc.rpt
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to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB3_1 (b) (b)
min1_10 11 6<- 0 0 FB3_2 STD 14 I/O (b)
min_5 2 0 /\1 2 FB3_3 STD 15 I/O (b)
min_4 2 0 0 3 FB3_4 STD (b) (b)
min_3 2 0 0 3 FB3_5 STD 17 I/O (b)
min_2 2 0 0 3 FB3_6 STD 18 I/O (b)
min_11 2 0 0 3 FB3_7 STD (b) (b)
min_10 2 0 0 3 FB3_8 STD 19 I/O (b)
min_1 2 0 0 3 FB3_9 STD 20 I/O (b)
min1_3 3 0 0 2 FB3_10 STD (b) (b)
min1_2 3 0 0 2 FB3_11 STD 21 I/O (b)
min1_1 3 0 \/2 0 FB3_12 STD 23 I/O (b)
min1_5 7 2<- 0 0 FB3_13 STD (b) (b)
(unused) 0 0 \/5 0 FB3_14 24 I/O (b)
min1_4 7 5<- \/3 0 FB3_15 STD 25 I/O (b)
min1_7 8 3<- 0 0 FB3_16 STD 26 I/O (b)
(unused) 0 0 \/5 0 FB3_17 31 I/O (b)
min1_8 10 5<- 0 0 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: flag 8: min1_4.FBK.LFBK 15: min_10.FBK.LFBK
2: min1_0 9: min1_5.FBK.LFBK 16: min_11.FBK.LFBK
3: min1_1.FBK.LFBK 10: min1_6 17: min_2.FBK.LFBK
4: min1_10.FBK.LFBK 11: min1_7.FBK.LFBK 18: min_3.FBK.LFBK
5: min1_11 12: min1_8.FBK.LFBK 19: min_4.FBK.LFBK
6: min1_2.FBK.LFBK 13: min1_9 20: min_5.FBK.LFBK
7: min1_3.FBK.LFBK 14: min_1.FBK.LFBK 21: sec
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
min1_10 XXXXXXXXXXXXX.......X................... 14 14
min_5 X.......X..........XX................... 4 4
min_4 X......X..........X.X................... 4 4
min_3 X.....X..........X..X................... 4 4
min_2 X....X..........X...X................... 4 4
min_11 X...X..........X....X................... 4 4
min_10 X..X..........X.....X................... 4 4
min_1 X.X..........X......X................... 4 4
min1_3 XXX..XX.............X................... 6 6
min1_2 XXX..XX.............X................... 6 6
min1_1 XXX...X.............X................... 5 5
min1_5 XXX..XXXX.X.........X................... 9 9
min1_4 XXX..XXXXXX.........X................... 10 10
min1_7 XXX..XXXXXX.........X................... 10 10
min1_8 XXXXXXXXXXXXX.......X................... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 19/17
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
count_1 1 0 0 4 FB4_10 STD (b) (b)
min_9 2 0 0 3 FB4_11 STD 66 I/O (b)
min_8 2 0 0 3 FB4_12 STD 67 I/O (b)
min_7 2 0 0 3 FB4_13 STD (b) (b)
min_6 2 0 0 3 FB4_14 STD 68 I/O (b)
min_15 2 0 0 3 FB4_15 STD 69 I/O (b)
min_14 2 0 0 3 FB4_16 STD (b) (b)
min_13 2 0 0 3 FB4_17 STD 70 I/O (b)
min_12 2 0 0 3 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 8: min1_7 14: min_15.FBK.LFBK
2: flag 9: min1_8 15: min_6.FBK.LFBK
3: min1_12 10: min1_9 16: min_7.FBK.LFBK
4: min1_13 11: min_12.FBK.LFBK 17: min_8.FBK.LFBK
5: min1_14 12: min_13.FBK.LFBK 18: min_9.FBK.LFBK
6: min1_15 13: min_14.FBK.LFBK 19: sec
7: min1_6
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_1 X....................................... 1 1
min_9 .X.......X.......XX..................... 4 4
min_8 .X......X.......X.X..................... 4 4
min_7 .X.....X.......X..X..................... 4 4
min_6 .X....X.......X...X..................... 4 4
min_15 .X...X.......X....X..................... 4 4
min_14 .X..X.......X.....X..................... 4 4
min_13 .X.X.......X......X..................... 4 4
min_12 .XX.......X.......X..................... 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\5 0 FB5_1 (b) (b)
(unused) 0 0 /\5 0 FB5_2 32 I/O (b)
flag 1 0 0 4 FB5_3 STD 33 I/O (b)
(unused) 0 0 0 5 FB5_4 (b)
min_0 2 0 0 3 FB5_5 STD 34 I/O (b)
min1_0 3 0 0 2 FB5_6 STD 35 I/O (b)
(unused) 0 0 \/5 0 FB5_7 (b) (b)
min1_9 10 5<- 0 0 FB5_8 STD 36 I/O (b)
(unused) 0 0 \/5 0 FB5_9 37 I/O (b)
(unused) 0 0 \/5 0 FB5_10 (b) (b)
(unused) 0 0 \/5 0 FB5_11 39 I/O (b)
lddat<0> 16 15<- \/4 0 FB5_12 STD 40 I/O O
(unused) 0 0 \/5 0 FB5_13 (b) (b)
lddat<1> 16 11<- 0 0 FB5_14 STD 41 I/O O
lddat<2> 12 9<- /\2 0 FB5_15 STD 43 I/O O
(unused) 0 0 /\5 0 FB5_16 (b) (b)
lddat<3> 16 15<- /\4 0 FB5_17 STD 44 I/O O
(unused) 0 0 /\5 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: count_10 12: min1_7 22: min_15
2: count_11 13: min1_8 23: min_2
3: flag.FBK.LFBK 14: min1_9.FBK.LFBK 24: min_3
4: min1_0.FBK.LFBK 15: min_0.FBK.LFBK 25: min_4
5: min1_1 16: min_1 26: min_5
6: min1_11 17: min_10 27: min_6
7: min1_2 18: min_11 28: min_7
8: min1_3 19: min_12 29: min_8
9: min1_4 20: min_13 30: min_9
10: min1_5 21: min_14 31: sec
11: min1_6
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
flag ..............................X......... 1 1
min_0 ..XX..........X...............X......... 4 4
min1_0 ..XXX.XX......................X......... 6 6
min1_9 ..XXXXXXXXXXXX................X......... 13 13
lddat<0> XX............XXXXXXXXXXXXXXXX.......... 18 18
lddat<1> XX............XXXXXXXXXXXXXXXX.......... 18 18
lddat<2> XX............XXXXXXXXXXXXXXXX.......... 18 18
lddat<3> XX............XXXXXXXXXXXXXXXX.......... 18 18
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/3 2 FB6_1 (b) (b)
lddat<4> 12 7<- 0 0 FB6_2 STD 45 I/O O
lddat<5> 1 0 /\4 0 FB6_3 STD 46 I/O O
count_9 1 0 \/4 0 FB6_4 STD (b) (b)
lddat<6> 12 7<- 0 0 FB6_5 STD 47 I/O O
lddat<7> 0 0 /\3 2 FB6_6 STD 48 I/O O
count_8 1 0 0 4 FB6_7 STD (b) (b)
ldsel<0> 1 0 0 4 FB6_8 STD 50 I/O O
ldsel<1> 1 0 0 4 FB6_9 STD 51 I/O O
count_7 1 0 0 4 FB6_10 STD (b) (b)
ldsel<2> 1 0 0 4 FB6_11 STD 52 I/O O
ldsel<3> 1 0 0 4 FB6_12 STD 53 I/O O
count_13 1 0 0 4 FB6_13 STD (b) (b)
count_12 1 0 0 4 FB6_14 STD 54 I/O (b)
count_10 1 0 \/2 2 FB6_15 STD 55 I/O (b)
(unused) 0 0 \/5 0 FB6_16 (b) (b)
lddat<5>_BUFR.MC 16 11<- 0 0 FB6_17 STD 56 I/O (b)
count_11 1 0 /\4 0 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 11: count_7.FBK.LFBK 21: min_14
2: count_1 12: count_8.FBK.LFBK 22: min_15
3: count_10.FBK.LFBK 13: count_9.FBK.LFBK 23: min_2
4: count_11.FBK.LFBK 14: "lddat<5>_BUFR.FBK".LFBK
24: min_3
5: count_12.FBK.LFBK 15: min_0 25: min_4
6: count_2 16: min_1 26: min_5
7: count_3 17: min_10 27: min_6
8: count_4 18: min_11 28: min_7
9: count_5 19: min_12 29: min_8
10: count_6 20: min_13 30: min_9
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
lddat<4> ..XX..........XXXXXXXXXXXXXXXX.......... 18 18
lddat<5> .............X.......................... 1 1
count_9 XX...XXXXXXX............................ 9 9
lddat<6> ..XX..........XXXXXXXXXXXXXXXX.......... 18 18
lddat<7> ........................................ 0 0
count_8 XX...XXXXXX............................. 8 8
ldsel<0> ..XX.................................... 2 2
ldsel<1> ..XX.................................... 2 2
count_7 XX...XXXXX.............................. 7 7
ldsel<2> ..XX.................................... 2 2
ldsel<3> ..XX.................................... 2 2
count_13 XXXXXXXXXXXXX........................... 13 13
count_12 XXXX.XXXXXXXX........................... 12 12
count_10 XX...XXXXXXXX........................... 10 10
lddat<5>_BUFR.MC ..XX..........XXXXXXXXXXXXXXXX.......... 18 18
count_11 XXX..XXXXXXXX........................... 11 11
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"lddat<0>" = /count_10 * count_11 * min_10 * min_11 * min_8 *
/min_9
;Imported pterms FB5_11
+ count_10 * count_11 * min_12 * min_13 * /min_14 *
min_15
+ count_10 * count_11 * min_12 * /min_13 * min_14 *
min_15
+ /count_10 * count_11 * min_10 * /min_11 * /min_8 *
/min_9
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