📄 __projnav.log
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SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_10"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_11"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_12"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_13"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_14"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_15"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_16"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_17"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_18"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_19"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_20"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_20 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_21"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_21 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_22"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_22 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_23"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_23 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_4"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_5"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_6"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_7"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_8"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_9"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "fosc.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "fosc.ngd" ...Writing NGDBUILD log file "fosc.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'
Creating TCL ProcessStarting: 'ChipView.bat -f fosc.ngd -uc fosc.ucf -dev XC95108-7-PC84'Tcl _chipview.tcl detected that program 'ChipView.bat -f fosc.ngd -uc fosc.ucf -dev XC95108-7-PC84' completed successfully.Starting: 'chkdate'Tcl _chipview.tcl detected that program 'chkdate' completed successfully.Existing implementation results (if any) will be retained.Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_fosc.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning fosc.v
Writing fosc.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Configure Device (iMPACT)
Starting: 'exewrap @__fosc_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn fosc.xst -ofn fosc.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn fosc.xst -ofn fosc.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : fosc.prj---- Target ParametersTarget Device : XC9500Output File Name : foscOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : foscAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : fosc.prjCompiling included source file 'fosc.v'Module <fosc> compiled.Continuing compilation of source file 'fosc.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'fosc.prj'No errors in compilationAnalysis of file <fosc.prj> succeeded. Starting Verilog synthesis. Analyzing top module <fosc>.WARNING:Xst:905 - "fosc.v", line 24: The signals <min> are missing in the sensitivity list of always block.Module <fosc> is correct for synthesis.Synthesizing Unit <fosc>. Related source file is fosc.v. Found 16x8-bit ROM for signal <lddat_reg>. Found 4-bit adder for signal <$n0000> created at line 69. Found 4-bit adder for signal <$n0001> created at line 73. Found 4-bit adder for signal <$n0002> created at line 77. Found 4-bit adder for signal <$n0003> created at line 81. Found 4-bit comparator greater for signal <$n0019> created at line 70. Found 4-bit comparator greater for signal <$n0020> created at line 74. Found 4-bit comparator greater for signal <$n0021> created at line 78. Found 4-bit comparator greater for signal <$n0022> created at line 82. Found 24-bit adder for signal <$old_count_1>. Found 24-bit register for signal <count>. Found 1-bit register for signal <flag>. Found 4-bit 4-to-1 multiplexer for signal <ledbuf>. Found 16-bit register for signal <min>. Found 16-bit register for signal <min1>. Found 1-bit register for signal <sec>. Summary: inferred 1 ROM(s). inferred 58 D-type flip-flop(s). inferred 5 Adder/Subtracter(s). inferred 4 Comparator(s). inferred 4 Multiplexer(s).⌨️ 快捷键说明
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