__projnav.log

xilinx实现4位频率计

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_fosc.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    fosc.v
Writing fosc.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_fosc.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    fosc.v
Writing fosc.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Assign Pins (ChipViewer)

Starting: 'exewrap @__fosc_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn fosc.xst -ofn fosc.syr'


Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn fosc.xst -ofn fosc.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : fosc.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : fosc
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : fosc
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : fosc.prj
Compiling included source file 'fosc.v'
Module <fosc> compiled.
Continuing compilation of source file 'fosc.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'fosc.prj'
No errors in compilation
Analysis of file <fosc.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <fosc>.
WARNING:Xst:905 - "fosc.v", line 24: The signals <min> are missing in the sensitivity list of always block.
Module <fosc> is correct for synthesis.

Synthesizing Unit <fosc>.
    Related source file is fosc.v.
    Found 16x8-bit ROM for signal <lddat_reg>.
    Found 4-bit adder for signal <$n0000> created at line 69.
    Found 4-bit adder for signal <$n0001> created at line 73.
    Found 4-bit adder for signal <$n0002> created at line 77.
    Found 4-bit adder for signal <$n0003> created at line 81.
    Found 4-bit comparator greater for signal <$n0019> created at line 70.
    Found 4-bit comparator greater for signal <$n0020> created at line 74.
    Found 4-bit comparator greater for signal <$n0021> created at line 78.
    Found 4-bit comparator greater for signal <$n0022> created at line 82.
    Found 24-bit adder for signal <$old_count_1>.
    Found 24-bit register for signal <count>.
    Found 1-bit register for signal <flag>.
    Found 4-bit 4-to-1 multiplexer for signal <ledbuf>.
    Found 16-bit register for signal <min>.
    Found 16-bit register for signal <min1>.
    Found 1-bit register for signal <sec>.
    Summary:
	inferred   1 ROM(s).
	inferred  58 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <fosc> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 20
  24-bit register                  : 1
  1-bit register                   : 18
  16-bit register                  : 1
# Multiplexers                     : 1
  4-bit 4-to-1 multiplexer         : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 4
  24-bit adder                     : 1
# Comparators                      : 4
  4-bit comparator greater         : 4

=========================================================================


Starting low level synthesis...

Optimizing unit <fosc> ...
=========================================================================
Final Results
Output File Name                   : fosc
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 4
  4-bit comparator greater         : 4
# Xors                             : 35
  1-bit xor2                       : 35

Design Statistics
# Edif Instances                   : 390
# I/Os                             : 14

=========================================================================
CPU : 4.01 / 4.23 s | Elapsed : 4.00 / 4.00 s
 
--> 
EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp fosc ngdbuild.rsp'


Creating TCL Process
Starting: 'ngdbuild -f ngdbuild.rsp'


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc fosc.ucf -p XC9500 fosc.ngc fosc.ngd 

Reading NGO file "F:/    /Xilinx/fosc/fosc.ngc" ...
Reading component libraries for design expansion...
Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_1"...
WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Re
sult_2"...
WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Re
sult_3"...
WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Re
sult_1"...
WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Re
sult_2"...
WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Re
sult_3"...
WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Re
sult_1"...
WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_2"...
WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Re
sult_3"...
WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Re
sult_1"...
WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_1 : All styles for