traffic.syr

xilinx完成一个模拟的十字路口交通信号灯

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : traffic.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : traffic
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : traffic
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : traffic.prj
Compiling included source file 'traffic.v'
Module <traffic> compiled.
Continuing compilation of source file 'traffic.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'traffic.prj'
No errors in compilation
Analysis of file <traffic.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <traffic>.
WARNING:Xst:854 - "traffic.v", line 18: Ignored initial statement.
WARNING:Xst:905 - "traffic.v", line 86: The signals <lamp_time> are missing in the sensitivity list of always block.
Module <traffic> is correct for synthesis.

Synthesizing Unit <traffic>.
    Related source file is traffic.v.
    Found 16x8-bit ROM for signal <seg_reg>.
    Found 8-bit subtractor for signal <$n0000> created at line 49.
    Found 4-bit comparator greater for signal <$n0019> created at line 78.
    Found 22-bit comparator less for signal <$n0024> created at line 26.
    Found 22-bit up counter for signal <count>.
    Found 2-bit register for signal <lamp_status>.
    Found 8-bit register for signal <lamp_time>.
    Found 8-bit register for signal <led_reg>.
    Found 3-bit up counter for signal <sec_tick>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <traffic> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 10
  2-bit register                   : 1
  1-bit register                   : 8
  8-bit register                   : 1
# Counters                         : 2
  22-bit up counter                : 1
  3-bit up counter                 : 1
# Adders/Subtractors               : 1
  8-bit subtractor                 : 1
# Comparators                      : 2
  4-bit comparator greater         : 1
  22-bit comparator less           : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <traffic> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : traffic
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 1
  4-bit comparator greater         : 1
# Xors                             : 30
  1-bit xor2                       : 30

Design Statistics
# Edif Instances                   : 388
# I/Os                             : 21

=========================================================================
CPU : 4.56 / 5.44 s | Elapsed : 4.00 / 4.00 s
 
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