📄 traffic.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: traffic Date: 11-22-2002, 10:46AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
55 /108 ( 50%) 403 /540 ( 74%) 43 /108 ( 39%) 21 /69 ( 30%) 149/216 ( 68%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 0 0 | I/O : 20 43
Output : 20 20 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 21 21
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 43
Non-registered Macrocell driving I/O 12
GLOBAL RESOURCES:
Signal 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 55 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 55 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
count_0 9 19 FB3_18 STD (b) (b)
count_1 11 20 FB4_2 STD 57 I/O (b)
count_10 11 21 FB4_14 STD 68 I/O (b)
count_11 11 22 FB2_9 STD 77 GTS/I/O (b)
count_12 13 22 FB1_4 STD (b) (b)
count_13 13 22 FB1_7 STD (b) (b)
count_14 13 22 FB1_10 STD (b) (b)
count_15 7 22 FB1_11 STD 7 I/O (b)
count_16 11 22 FB2_17 STD 84 I/O (b)
count_17 11 22 FB2_12 STD 80 I/O (b)
count_18 4 22 FB2_16 STD 83 I/O (b)
count_19 10 22 FB2_15 STD 82 I/O (b)
count_2 12 21 FB2_6 STD 75 I/O (b)
count_20 0 0 FB3_8 STD 19 I/O (b)
count_21 0 0 FB3_7 STD (b) (b)
count_3 13 22 FB2_2 STD 71 I/O (b)
count_4 14 22 FB1_14 STD 10 GCK/I/O (b)
count_5 15 22 FB6_10 STD (b) (b)
count_6 15 22 FB1_18 STD (b) (b)
count_7 16 22 FB6_14 STD 54 I/O (b)
count_8 16 22 FB6_18 STD (b) (b)
count_9 11 20 FB4_11 STD 66 I/O (b)
lamp_status_0 2 10 FB3_9 STD 20 I/O (b)
lamp_status_1 3 11 FB3_11 STD 21 I/O (b)
lamp_time_0 5 11 FB3_13 STD (b) (b)
lamp_time_1 12 11 FB5_18 STD (b) (b)
lamp_time_2 11 11 FB5_4 STD (b) (b)
lamp_time_3 6 11 FB5_7 STD (b) (b)
lamp_time_4 6 11 FB3_16 STD 26 I/O (b)
lamp_time_5 6 11 FB3_14 STD 24 I/O (b)
lamp_time_6 5 11 FB3_12 STD 23 I/O (b)
lamp_time_7 3 11 FB3_10 STD (b) (b)
led<0> 3 12 FB3_17 STD FAST 31 I/O O
led<1> 4 12 FB5_2 STD FAST 32 I/O O
led<2> 3 12 FB5_3 STD FAST 33 I/O O
led<3> 3 12 FB5_5 STD FAST 34 I/O O
led<4> 3 12 FB5_6 STD FAST 35 I/O O
led<5> 3 12 FB5_8 STD FAST 36 I/O O
led<6> 4 12 FB5_9 STD FAST 37 I/O O
led<7> 3 12 FB5_11 STD FAST 39 I/O O
sec_tick_0 9 18 FB3_2 STD 14 I/O (b)
sec_tick_1 9 19 FB4_15 STD 69 I/O (b)
sec_tick_2 9 20 FB4_10 STD (b) (b)
slcs<0> 1 2 FB6_8 STD FAST 50 I/O O
slcs<1> 1 2 FB6_9 STD FAST 51 I/O O
slcs<2> 1 2 FB6_11 STD FAST 52 I/O O
slcs<3> 1 2 FB6_12 STD FAST 53 I/O O
sled<0> 8 10 FB5_12 STD FAST 40 I/O O
sled<1> 8 10 FB5_14 STD FAST 41 I/O O
sled<2> 6 10 FB5_15 STD FAST 43 I/O O
sled<3> 8 10 FB5_17 STD FAST 44 I/O O
sled<4> 6 10 FB6_2 STD FAST 45 I/O O
sled<5> 8 10 FB6_3 STD FAST 46 I/O O
sled<6> 7 10 FB6_5 STD FAST 47 I/O O
sled<7> 0 0 FB6_6 STD FAST 48 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clock FB1_12 9 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 22 22 75 0/0 12
FB2 7 22 22 72 0/0 12
FB3 12 31 31 51 1/0 12
FB4 5 24 24 51 0/0 11
FB5 14 20 20 82 11/0 11
FB6 11 30 30 72 8/0 11
---- ----- ----- -----
55 403 20/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 22/14
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\5 0 FB1_1 (b) (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 \/3 2 FB1_3 2 I/O (b)
count_12 13 8<- 0 0 FB1_4 STD (b) (b)
(unused) 0 0 /\5 0 FB1_5 3 I/O (b)
(unused) 0 0 \/5 0 FB1_6 4 I/O (b)
count_13 13 8<- 0 0 FB1_7 STD (b) (b)
(unused) 0 0 /\3 2 FB1_8 5 I/O (b)
(unused) 0 0 \/5 0 FB1_9 6 I/O (b)
count_14 13 8<- 0 0 FB1_10 STD (b) (b)
count_15 7 5<- /\3 0 FB1_11 STD 7 I/O (b)
(unused) 0 0 /\5 0 FB1_12 9 GCK/I/O GCK
(unused) 0 0 \/5 0 FB1_13 (b) (b)
count_4 14 9<- 0 0 FB1_14 STD 10 GCK/I/O (b)
(unused) 0 0 /\4 1 FB1_15 11 I/O (b)
(unused) 0 0 0 5 FB1_16 12 GCK/I/O
(unused) 0 0 \/5 0 FB1_17 13 I/O (b)
count_6 15 10<- 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 9: count_16 16: count_3
2: count_1 10: count_17 17: count_4.FBK.LFBK
3: count_10 11: count_18 18: count_5
4: count_11 12: count_19 19: count_6.FBK.LFBK
5: count_12.FBK.LFBK 13: count_2 20: count_7
6: count_13.FBK.LFBK 14: count_20 21: count_8
7: count_14.FBK.LFBK 15: count_21 22: count_9
8: count_15.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_12 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_13 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_14 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_15 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_4 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_6 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 22/14
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB2_1 (b) (b)
count_3 13 8<- 0 0 FB2_2 STD 71 I/O (b)
(unused) 0 0 /\3 2 FB2_3 72 I/O (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 \/2 3 FB2_5 74 GSR/I/O (b)
count_2 12 7<- 0 0 FB2_6 STD 75 I/O (b)
(unused) 0 0 /\5 0 FB2_7 (b) (b)
(unused) 0 0 \/5 0 FB2_8 76 GTS/I/O (b)
count_11 11 6<- 0 0 FB2_9 STD 77 GTS/I/O (b)
(unused) 0 0 /\1 4 FB2_10 (b) (b)
(unused) 0 0 \/1 4 FB2_11 79 I/O (b)
count_17 11 6<- 0 0 FB2_12 STD 80 I/O (b)
(unused) 0 0 /\5 0 FB2_13 (b) (b)
(unused) 0 0 \/5 0 FB2_14 81 I/O (b)
count_19 10 5<- 0 0 FB2_15 STD 82 I/O (b)
count_18 4 0 \/1 0 FB2_16 STD 83 I/O (b)
count_16 11 6<- 0 0 FB2_17 STD 84 I/O (b)
(unused) 0 0 /\5 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: count_0 9: count_16.FBK.LFBK 16: count_3.FBK.LFBK
2: count_1 10: count_17.FBK.LFBK 17: count_4
3: count_10 11: count_18.FBK.LFBK 18: count_5
4: count_11.FBK.LFBK 12: count_19.FBK.LFBK 19: count_6
5: count_12 13: count_2.FBK.LFBK 20: count_7
6: count_13 14: count_20 21: count_8
7: count_14 15: count_21 22: count_9
8: count_15
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
count_3 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_2 XXXXXXXXXXXXXXX.XXXXXX.................. 21 21
count_11 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_17 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_19 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_18 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
count_16 XXXXXXXXXXXXXXXXXXXXXX.................. 22 22
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\4 1 FB3_1 (b) (b)
sec_tick_0 9 4<- 0 0 FB3_2 STD 14 I/O (b)
(unused) 0 0 /\4 1 FB3_3 15 I/O (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 17 I/O
(unused) 0 0 0 5 FB3_6 18 I/O
count_21 0 0 0 5 FB3_7 STD (b) (b)
count_20 0 0 0 5 FB3_8 STD 19 I/O (b)
lamp_status_0 2 0 0 3 FB3_9 STD 20 I/O (b)
lamp_time_7 3 0 0 2 FB3_10 STD (b) (b)
lamp_status_1 3 0 0 2 FB3_11 STD 21 I/O (b)
lamp_time_6 5 0 0 0 FB3_12 STD 23 I/O (b)
lamp_time_0 5 0 0 0 FB3_13 STD (b) (b)
lamp_time_5 6 1<- 0 0 FB3_14 STD 24 I/O (b)
(unused) 0 0 /\1 4 FB3_15 25 I/O (b)
lamp_time_4 6 1<- 0 0 FB3_16 STD 26 I/O (b)
led<0> 3 0 /\1 1 FB3_17 STD 31 I/O O
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