📄 __projnav.log
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JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_traffic2.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning traffic2.v
Writing traffic2.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_traffic.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning traffic.v
Writing traffic.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_traffic.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning traffic.v
Writing traffic.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Implement Design
Starting: 'exewrap @__traffic_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn traffic.xst -ofn traffic.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn traffic.xst -ofn traffic.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.88 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.88 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : traffic.prj---- Target ParametersTarget Device : XC9500Output File Name : trafficOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : trafficAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : traffic.prjCompiling included source file 'traffic.v'Module <traffic> compiled.Continuing compilation of source file 'traffic.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'traffic.prj'No errors in compilationAnalysis of file <traffic.prj> succeeded. Starting Verilog synthesis. Analyzing top module <traffic>.WARNING:Xst:854 - "traffic.v", line 18: Ignored initial statement.WARNING:Xst:905 - "traffic.v", line 86: The signals <lamp_time> are missing in the sensitivity list of always block.Module <traffic> is correct for synthesis.Synthesizing Unit <traffic>. Related source file is traffic.v. Found 16x8-bit ROM for signal <seg_reg>. Found 8-bit subtractor for signal <$n0000> created at line 49. Found 4-bit comparator greater for signal <$n0019> created at line 78. Found 22-bit comparator less for signal <$n0024> created at line 26. Found 22-bit up counter for signal <count>. Found 2-bit register for signal <lamp_status>. Found 8-bit register for signal <lamp_time>. Found 8-bit register for signal <led_reg>. Found 3-bit up counter for signal <sec_tick>. Summary: inferred 1 ROM(s). inferred 2 Counter(s). inferred 18 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s).Unit <traffic> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Registers : 10 2-bit register : 1 1-bit register : 8 8-bit register : 1# Counters : 2 22-bit up counter : 1 3-bit up counter : 1# Adders/Subtractors : 1 8-bit subtractor : 1# Comparators : 2 4-bit comparator greater : 1 22-bit comparator less : 1=========================================================================Starting low level synthesis...Optimizing unit <traffic> ...Merging netlists...=========================================================================Final ResultsOutput File Name : trafficOutput Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Comparators : 1 4-bit comparator greater : 1# Xors : 30 1-bit xor2 : 30Design Statistics# Edif Instances : 388# I/Os : 21=========================================================================CPU : 4.56 / 5.44 s | Elapsed : 4.00 / 4.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp traffic ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc traffic.ucf -p XC9500 traffic.ngctraffic.ngd Reading NGO file "F:/ /Xilinx/traffic/traffic.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_10"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_11"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_12"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_13"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_14"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_15"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_16"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_17"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_18"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_19"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_20"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_20 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_21"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_21 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_8"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_9"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Msub__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module Msub__n0000_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "sec_tick_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module sec_tick_Madd__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "sec_tick_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module sec_tick_Madd__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "traffic.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "traffic.ngd" ...Writing NGDBUILD log file "traffic.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'
Creating TCL ProcessStarting: 'cpldfit -f _cpldfit.rsp traffic.ngd'Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Considering device XC95108-PC84.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 55 equations into 6 function blocks...........Design traffic has been optimized and fit into device XC95108-7-PC84.Tcl _cpldfit.tcl detected that program 'cpldfit -f _cpldfit.rsp traffic.ngd' completed successfully.Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Configure Device (iMPACT)
Starting: 'exewrap -mode pipe -tapkeep -command hprep6 -i traffic -r int -a -l traffic.log -n traffic '
Starting: 'hprep6 -i traffic -r int -a -l traffic.log -n traffic 'Release 4.1WP3.x - Programming File Generator E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.EXEWRAP detected that program 'hprep6' completed successfully.Done: completed successfully.
Launching: 'impact -f __impact.rsp'
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