📄 ledwater.rpt
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(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 30/6
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
buffer_21 1 0 0 4 FB5_1 STD (b) (b)
ledout<1> 2 0 0 3 FB5_2 STD 32 I/O O
ledout<2> 2 0 0 3 FB5_3 STD 33 I/O O
buffer_20 1 0 0 4 FB5_4 STD (b) (b)
ledout<3> 2 0 0 3 FB5_5 STD 34 I/O O
ledout<4> 2 0 0 3 FB5_6 STD 35 I/O O
buffer_19 1 0 0 4 FB5_7 STD (b) (b)
ledout<5> 2 0 0 3 FB5_8 STD 36 I/O O
ledout<6> 2 0 0 3 FB5_9 STD 37 I/O O
buffer_18 1 0 \/2 2 FB5_10 STD (b) (b)
ledout<7> 2 2<- \/5 0 FB5_11 STD 39 I/O I/O
ledout<8> 23 18<- 0 0 FB5_12 STD 40 I/O O
(unused) 0 0 /\5 0 FB5_13 (b) (b)
(unused) 0 0 /\5 0 FB5_14 41 I/O (b)
buffer_17 1 0 /\3 1 FB5_15 STD 43 I/O (b)
buffer_16 1 0 0 4 FB5_16 STD (b) (b)
buffer_15 1 0 0 4 FB5_17 STD 44 I/O (b)
buffer_14 1 0 0 4 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N116.FBK.LFBK 11: buffer_11 21: buffer_20.FBK.LFBK
2: N118.FBK.LFBK 12: buffer_12 22: buffer_21.FBK.LFBK
3: N120.FBK.LFBK 13: buffer_13 23: buffer_3
4: N122.FBK.LFBK 14: buffer_14.FBK.LFBK
24: buffer_4
5: N124.FBK.LFBK 15: buffer_15.FBK.LFBK
25: buffer_5
6: N126.FBK.LFBK 16: buffer_16.FBK.LFBK
26: buffer_6
7: N128.FBK.LFBK 17: buffer_17.FBK.LFBK
27: buffer_7
8: buffer_0 18: buffer_18.FBK.LFBK
28: buffer_8
9: buffer_1 19: buffer_19.FBK.LFBK
29: buffer_9
10: buffer_10 20: buffer_2 30: "ledout<0>".PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
buffer_21 .......XXXXXXXXXXXXXX.XXXXXXX........... 21 21
ledout<1> X......XXXXXXXXXXXXXXXXXXXXXXX.......... 24 24
ledout<2> XX.....XXXXXXXXXXXXXXXXXXXXXX........... 24 24
buffer_20 .......XXXXXXXXXXXXX..XXXXXXX........... 20 20
ledout<3> .XX....XXXXXXXXXXXXXXXXXXXXXX........... 24 24
ledout<4> ..XX...XXXXXXXXXXXXXXXXXXXXXX........... 24 24
buffer_19 .......XXXXXXXXXXX.X..XXXXXXX........... 19 19
ledout<5> ...XX..XXXXXXXXXXXXXXXXXXXXXX........... 24 24
ledout<6> ....XX.XXXXXXXXXXXXXXXXXXXXXX........... 24 24
buffer_18 .......XXXXXXXXXX..X..XXXXXXX........... 18 18
ledout<7> .....XXXXXXXXXXXXXXXXXXXXXXXX........... 24 24
ledout<8> ......XXXXXXXXXXXXXXXXXXXXXXXX.......... 24 24
buffer_17 .......XXXXXXXXX...X..XXXXXXX........... 17 17
buffer_16 .......XXXXXXXX....X..XXXXXXX........... 16 16
buffer_15 .......XXXXXXX.....X..XXXXXXX........... 15 15
buffer_14 .......XXXXXX......X..XXXXXXX........... 14 14
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 45 I/O
(unused) 0 0 0 5 FB6_3 46 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O
(unused) 0 0 0 5 FB6_6 48 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 50 I/O
(unused) 0 0 0 5 FB6_9 51 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 52 I/O
(unused) 0 0 0 5 FB6_12 53 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O
(unused) 0 0 0 5 FB6_15 55 I/O
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 56 I/O
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"ledout<1>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
N116.FBK.LFBK * buffer_14.FBK.LFBK * buffer_15.FBK.LFBK *
buffer_16.FBK.LFBK * buffer_17.FBK.LFBK * buffer_18.FBK.LFBK *
buffer_19.FBK.LFBK * buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK *
/"ledout<0>".PIN
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
/N116.FBK.LFBK * buffer_14.FBK.LFBK * buffer_15.FBK.LFBK *
buffer_16.FBK.LFBK * buffer_17.FBK.LFBK * buffer_18.FBK.LFBK *
buffer_19.FBK.LFBK * buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK *
"ledout<0>".PIN
"ledout<1>".CLKF = clk ;FCLK/GCK
"ledout<1>".PRLD = GND
"ledout<2>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
N116.FBK.LFBK * buffer_14.FBK.LFBK * buffer_15.FBK.LFBK *
buffer_16.FBK.LFBK * buffer_17.FBK.LFBK * buffer_18.FBK.LFBK *
buffer_19.FBK.LFBK * buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK *
/N118.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
/N116.FBK.LFBK * buffer_14.FBK.LFBK * buffer_15.FBK.LFBK *
buffer_16.FBK.LFBK * buffer_17.FBK.LFBK * buffer_18.FBK.LFBK *
buffer_19.FBK.LFBK * buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK *
N118.FBK.LFBK
"ledout<2>".CLKF = clk ;FCLK/GCK
"ledout<2>".PRLD = GND
"ledout<3>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * N118.FBK.LFBK *
/N120.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * /N118.FBK.LFBK *
N120.FBK.LFBK
"ledout<3>".CLKF = clk ;FCLK/GCK
"ledout<3>".PRLD = GND
"ledout<4>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * N120.FBK.LFBK *
/N122.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * /N120.FBK.LFBK *
N122.FBK.LFBK
"ledout<4>".CLKF = clk ;FCLK/GCK
"ledout<4>".PRLD = GND
"ledout<5>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * N122.FBK.LFBK *
/N124.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * /N122.FBK.LFBK *
N124.FBK.LFBK
"ledout<5>".CLKF = clk ;FCLK/GCK
"ledout<5>".PRLD = GND
"ledout<6>".T = /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * N124.FBK.LFBK *
/N126.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * /N124.FBK.LFBK *
N126.FBK.LFBK
"ledout<6>".CLKF = clk ;FCLK/GCK
"ledout<6>".PRLD = GND
"ledout<7>".T = ;Imported pterms FB5_10
/buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * N126.FBK.LFBK *
/N128.FBK.LFBK
+ /buffer_0 * buffer_1 * buffer_10 * buffer_11 *
buffer_12 * buffer_13 * buffer_2 * buffer_3 * buffer_4 *
buffer_5 * buffer_6 * buffer_7 * buffer_8 * buffer_9 *
buffer_14.FBK.LFBK * buffer_15.FBK.LFBK * buffer_16.FBK.LFBK *
buffer_17.FBK.LFBK * buffer_18.FBK.LFBK * buffer_19.FBK.LFBK *
buffer_20.FBK.LFBK * /buffer_21.FBK.LFBK * /N126.FBK.LFBK *
N128.FBK.LFBK
"ledout<7>".CLKF = clk ;FCLK/GCK
"ledout<7>".PRLD = GND
buffer_0 := /buffer_0.FBK.LFBK
buffer_0.CLKF = clk ;FCLK/GCK
buffer_0.PRLD = GND
buffer_1.T = buffer_0.FBK.LFBK
buffer_1.CLKF = clk ;FCLK/GCK
buffer_1.PRLD = GND
buffer_10.T = buffer_0.FBK.LFBK * buffer_1.FBK.LFBK *
buffer_2.FBK.LFBK * buffer_3.FBK.LFBK * buffer_4.FBK.LFBK *
buffer_5.FBK.LFBK * buffer_6.FBK.LFBK * buffer_7.FBK.LFBK *
buffer_8.FBK.LFBK * buffer_9.FBK.LFBK
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