📄 ledwater.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: ledwater Date: 11-20-2002, 4:45PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
31 /108 ( 28%) 61 /540 ( 11%) 31 /108 ( 28%) 10 /69 ( 14%) 54 /216 ( 25%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 0 0 | I/O : 9 54
Output : 7 7 | GCK/IO : 1 2
Bidirectional : 2 2 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 10 10
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 31
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 31 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 31 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
buffer_0 1 1 FB3_18 STD (b) (b)
buffer_1 1 1 FB3_16 STD 26 I/O (b)
buffer_10 1 10 FB3_15 STD 25 I/O (b)
buffer_11 1 11 FB3_14 STD 24 I/O (b)
buffer_12 1 12 FB3_13 STD (b) (b)
buffer_13 1 13 FB3_12 STD 23 I/O (b)
buffer_14 1 14 FB5_18 STD (b) (b)
buffer_15 1 15 FB5_17 STD 44 I/O (b)
buffer_16 1 16 FB5_16 STD (b) (b)
buffer_17 1 17 FB5_15 STD 43 I/O (b)
buffer_18 1 18 FB5_10 STD (b) (b)
buffer_19 1 19 FB5_7 STD (b) (b)
buffer_2 1 2 FB3_11 STD 21 I/O (b)
buffer_20 1 20 FB5_4 STD (b) (b)
buffer_21 1 21 FB5_1 STD (b) (b)
buffer_3 1 3 FB3_10 STD (b) (b)
buffer_4 1 4 FB3_9 STD 20 I/O (b)
buffer_5 1 5 FB3_8 STD 19 I/O (b)
buffer_6 1 6 FB3_7 STD (b) (b)
buffer_7 1 7 FB3_6 STD 18 I/O (b)
buffer_8 1 8 FB3_5 STD 17 I/O (b)
buffer_9 1 9 FB3_4 STD (b) (b)
ledout<0> 2 24 FB3_17 STD FAST 31 I/O I/O
ledout<1> 2 24 FB5_2 STD FAST 32 I/O O
ledout<2> 2 24 FB5_3 STD FAST 33 I/O O
ledout<3> 2 24 FB5_5 STD FAST 34 I/O O
ledout<4> 2 24 FB5_6 STD FAST 35 I/O O
ledout<5> 2 24 FB5_8 STD FAST 36 I/O O
ledout<6> 2 24 FB5_9 STD FAST 37 I/O O
ledout<7> 2 24 FB5_11 STD FAST 39 I/O I/O
ledout<8> 23 24 FB5_12 STD FAST 40 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_12 9 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 12
FB2 0 0 0 0 0/0 12
FB3 15 24 24 16 0/1 12
FB4 0 0 0 0 0/0 11
FB5 16 30 30 45 7/1 11
FB6 0 0 0 0 0/0 11
---- ----- ----- -----
31 61 7/2 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 7 I/O
(unused) 0 0 0 5 FB1_12 9 GCK/I/O GCK
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 10 GCK/I/O
(unused) 0 0 0 5 FB1_15 11 I/O
(unused) 0 0 0 5 FB1_16 12 GCK/I/O
(unused) 0 0 0 5 FB1_17 13 I/O
(unused) 0 0 0 5 FB1_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
(unused) 0 0 0 5 FB2_3 72 I/O
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 74 GSR/I/O
(unused) 0 0 0 5 FB2_6 75 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 76 GTS/I/O
(unused) 0 0 0 5 FB2_9 77 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 79 I/O
(unused) 0 0 0 5 FB2_12 80 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 82 I/O
(unused) 0 0 0 5 FB2_16 83 I/O
(unused) 0 0 0 5 FB2_17 84 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 24/12
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 14 I/O
(unused) 0 0 0 5 FB3_3 15 I/O
buffer_9 1 0 0 4 FB3_4 STD (b) (b)
buffer_8 1 0 0 4 FB3_5 STD 17 I/O (b)
buffer_7 1 0 0 4 FB3_6 STD 18 I/O (b)
buffer_6 1 0 0 4 FB3_7 STD (b) (b)
buffer_5 1 0 0 4 FB3_8 STD 19 I/O (b)
buffer_4 1 0 0 4 FB3_9 STD 20 I/O (b)
buffer_3 1 0 0 4 FB3_10 STD (b) (b)
buffer_2 1 0 0 4 FB3_11 STD 21 I/O (b)
buffer_13 1 0 0 4 FB3_12 STD 23 I/O (b)
buffer_12 1 0 0 4 FB3_13 STD (b) (b)
buffer_11 1 0 0 4 FB3_14 STD 24 I/O (b)
buffer_10 1 0 0 4 FB3_15 STD 25 I/O (b)
buffer_1 1 0 0 4 FB3_16 STD 26 I/O (b)
ledout<0> 2 0 0 3 FB3_17 STD 31 I/O I/O
buffer_0 1 0 0 4 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: buffer_0.FBK.LFBK 9: buffer_16 17: buffer_4.FBK.LFBK
2: buffer_1.FBK.LFBK 10: buffer_17 18: buffer_5.FBK.LFBK
3: buffer_10.FBK.LFBK
11: buffer_18 19: buffer_6.FBK.LFBK
4: buffer_11.FBK.LFBK
12: buffer_19 20: buffer_7.FBK.LFBK
5: buffer_12.FBK.LFBK
13: buffer_2.FBK.LFBK 21: buffer_8.FBK.LFBK
6: buffer_13.FBK.LFBK
14: buffer_20 22: buffer_9.FBK.LFBK
7: buffer_14 15: buffer_21 23: "ledout<7>".PIN
8: buffer_15 16: buffer_3.FBK.LFBK 24: n0000.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
buffer_9 XX..........X..XXXXXX................... 9 9
buffer_8 XX..........X..XXXXX.................... 8 8
buffer_7 XX..........X..XXXX..................... 7 7
buffer_6 XX..........X..XXX...................... 6 6
buffer_5 XX..........X..XX....................... 5 5
buffer_4 XX..........X..X........................ 4 4
buffer_3 XX..........X........................... 3 3
buffer_2 XX...................................... 2 2
buffer_13 XXXXX.......X..XXXXXXX.................. 13 13
buffer_12 XXXX........X..XXXXXXX.................. 12 12
buffer_11 XXX.........X..XXXXXXX.................. 11 11
buffer_10 XX..........X..XXXXXXX.................. 10 10
buffer_1 X....................................... 1 1
ledout<0> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
buffer_0 X....................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
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