ledwater.v

利用xilinx

module ledwater (ledout,clk);
    output [8:0] ledout;
	 input clk;
	 reg[8:0] ledout;
	 reg[21:0] buffer;

 initial 
	ledout=9'b111111111;

always@(posedge clk)
    begin
	 	buffer=buffer+1;
	 	if(buffer==22'b111111111111111111111)
  			begin
		   	ledout=ledout<<1;
				if(ledout==9'b000000000)
					ledout=9'b111111111;
			end
	 end
endmodule