📄 __projnav.log
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Updating: Configure Device (iMPACT)
Starting: 'exewrap @__ledwater_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : ledwater.prj---- Target ParametersTarget Device : XC9500Output File Name : ledwaterOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : ledwaterAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : ledwater.prjCompiling included source file 'ledwater.v'Module <ledwater> compiled.Continuing compilation of source file 'ledwater.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'ledwater.prj'No errors in compilationAnalysis of file <ledwater.prj> succeeded. Starting Verilog synthesis. Analyzing top module <ledwater>.WARNING:Xst:854 - "ledwater.v", line 7: Ignored initial statement.Module <ledwater> is correct for synthesis.Synthesizing Unit <ledwater>. Related source file is ledwater.v. Found 9-bit register for signal <ledout>. Found 22-bit adder for signal <$old_buffer_1>. Found 22-bit register for signal <buffer>. Summary: inferred 31 D-type flip-flop(s). inferred 1 Adder/Subtracter(s).Unit <ledwater> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 2 22-bit register : 1 9-bit register : 1# Adders/Subtractors : 1 22-bit adder : 1=========================================================================Starting low level synthesis...Optimizing unit <ledwater> ...=========================================================================Final ResultsOutput File Name : ledwaterOutput Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Xors : 21 1-bit xor2 : 21Design Statistics# Edif Instances : 129# I/Os : 10=========================================================================CPU : 2.03 / 2.20 s | Elapsed : 2.00 / 2.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp ledwater ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc ledwater.ucf -p XC9500 ledwater.ngcledwater.ngd Reading NGO file "F:/ /Xilinx/ledwater/ledwater.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_10"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_11"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_12"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_13"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_14"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_15"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_16"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_17"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_18"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_19"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_20"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_20 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_21"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_21 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_4"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_5"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_6"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_7"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_8"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_9"...WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "ledwater.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "ledwater.ngd" ...Writing NGDBUILD log file "ledwater.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'
Creating TCL ProcessStarting: 'cpldfit -f _cpldfit.rsp ledwater.ngd'Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Considering device XC95108-PC84.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 31 equations into 6 function blocks...Design ledwater has been optimized and fit into device XC95108-7-PC84.Tcl _cpldfit.tcl detected that program 'cpldfit -f _cpldfit.rsp ledwater.ngd' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command hprep6 -i ledwater -r int -a -l ledwater.log -n ledwater '
Starting: 'hprep6 -i ledwater -r int -a -l ledwater.log -n ledwater 'Release 4.1WP3.x - Programming File Generator E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.EXEWRAP detected that program 'hprep6' completed successfully.Done: completed successfully.
Launching: 'impact -f __impact.rsp'
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_ledwater.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning ledwater.v
Writing ledwater.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Configure Device (iMPACT)
Starting: 'exewrap @__ledwater_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : ledwater.prj---- Target ParametersTarget Device : XC9500⌨️ 快捷键说明
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