ledwater.syr

利用xilinx

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : ledwater.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : ledwater
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : ledwater
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : ledwater.prj
Compiling included source file 'ledwater.v'
Module <ledwater> compiled.
Continuing compilation of source file 'ledwater.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'ledwater.prj'
No errors in compilation
Analysis of file <ledwater.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <ledwater>.
WARNING:Xst:854 - "ledwater.v", line 7: Ignored initial statement.
ERROR:Xst:880 - "ledwater.v", line 16: Cannot mix blocking and non blocking assignments on signal <ledout>.
ERROR:Xst:880 - "ledwater.v", line 16: Cannot mix blocking and non blocking assignments on signal <ledout>.
 
Found 2 error(s). Aborting synthesis.
CPU : 0.83 / 0.99 s | Elapsed : 1.00 / 1.00 s
 
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