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1 GLB Level(s)
COUNT0[0].D = !COUNT0[0] & !LOAD
COUNT0[0].C = CARRY
COUNT0[0].R =
GLB glb11, A0
1 Input(s)
(glb02.O3, STATE_C[1], I15)
1 Output(s)
(STATE_C[1]_buff1, O1)
1 Product Term(s)
Output STATE_C[1]_buff1
1 Input(s)
STATE_C[1]
1 Fanout(s)
glb00.I14
1 Product Term(s)
1 GLB Level(s)
STATE_C[1]_buff1 = STATE_C[1]
GLB glb12, B0
4 Input(s)
(glb06.O0, AND_1071, I8), (glb06.O1, AND_1069, I9), (glb06.O2,
AND_1068, I10), (glb06.O3, AND_1070, I11)
4 Output(s)
(AND_1071_buff1, O0), (AND_1069_buff1, O1),
(AND_1068_buff1, O2), (AND_1070_buff1, O3)
4 Product Term(s)
Output AND_1071_buff1
1 Input(s)
AND_1071
1 Fanout(s)
SELOUT(3).IR
1 Product Term(s)
2 GLB Level(s)
AND_1071_buff1 = AND_1071
Output AND_1069_buff1
1 Input(s)
AND_1069
1 Fanout(s)
SELOUT(2).IR
1 Product Term(s)
2 GLB Level(s)
AND_1069_buff1 = AND_1069
Output AND_1068_buff1
1 Input(s)
AND_1068
1 Fanout(s)
SELOUT(1).IR
1 Product Term(s)
2 GLB Level(s)
AND_1068_buff1 = AND_1068
Output AND_1070_buff1
1 Input(s)
AND_1070
1 Fanout(s)
SELOUT(0).IR
1 Product Term(s)
2 GLB Level(s)
AND_1070_buff1 = AND_1070
GLB glb13, D0
3 Input(s)
(glb04.O1, N_145_I, I10), (glb04.O0, N_155_I, I11), (glb04.O3,
VCC_1283, I8)
3 Output(s)
(N_155_I_buff1, O0), (N_145_I_buff1, O1), (VCC_1283_buff1, O3)
3 Product Term(s)
Output N_155_I_buff1
1 Input(s)
N_155_I
1 Fanout(s)
SEGOUT(3).IR
1 Product Term(s)
2 GLB Level(s)
N_155_I_buff1 = N_155_I
Output N_145_I_buff1
1 Input(s)
N_145_I
1 Fanout(s)
SEGOUT(6).IR
1 Product Term(s)
2 GLB Level(s)
N_145_I_buff1 = N_145_I
Output VCC_1283_buff1
1 Input(s)
VCC_1283
1 Fanout(s)
SEGOUT(0).IR
1 Product Term(s)
1 GLB Level(s)
VCC_1283_buff1 = VCC_1283
Clock Input CLK, Y0
Output CLKX
3 Fanout(s)
glb07.CLK0, glb01.CLK0, glb03.CLK0
Clock Input CLK1, Y2
Output CLK1X
1 Fanout(s)
glb08.CLK2
Output G1, IO45
Input (glb01.O1, AND_1072)
G1 = !AND_1072
Output G2, IO42
Input (glb01.O2, AND_1074)
G2 = !AND_1074
Output R1, IO47
Input (glb02.O3, STATE_C[1])
R1 = STATE_C[1]
Output R2, IO44
Input (glb02.O0, DEF_1233)
R2 = !DEF_1233
Output SEGOUT(0), IO55
Input (glb13.O3, VCC_1283_buff1)
SEGOUT(0) = VCC_1283_buff1
Output SEGOUT(1), IO54
Input (glb05_part2.O2, OR_763)
SEGOUT(1) = OR_763
Output SEGOUT(2), IO53
Input (glb05_part1.O1, OR_759)
SEGOUT(2) = OR_759
Output SEGOUT(3), IO52
Input (glb13.O0, N_155_I_buff1)
SEGOUT(3) = N_155_I_buff1
Output SEGOUT(4), IO51
Input (glb03.O3, N_148_I)
SEGOUT(4) = N_148_I
Output SEGOUT(5), IO50
Input (glb03.O2, N_150_I)
SEGOUT(5) = N_150_I
Output SEGOUT(6), IO49
Input (glb13.O1, N_145_I_buff1)
SEGOUT(6) = N_145_I_buff1
Output SEGOUT(7), IO48
Input (glb03.O0, N_143_I)
SEGOUT(7) = N_143_I
Output SELOUT(0), IO19
Input (glb12.O3, AND_1070_buff1)
SELOUT(0) = !AND_1070_buff1
Output SELOUT(1), IO18
Input (glb12.O2, AND_1068_buff1)
SELOUT(1) = !AND_1068_buff1
Output SELOUT(2), IO17
Input (glb12.O1, AND_1069_buff1)
SELOUT(2) = !AND_1069_buff1
Output SELOUT(3), IO16
Input (glb12.O0, AND_1071_buff1)
SELOUT(3) = !AND_1071_buff1
Output Y1, IO46
Input (glb02.O2, AND_1075)
Y1 = !AND_1075
Output Y2, IO43
Input (glb01.O3, AND_1073)
Y2 = !AND_1073
Clock Assignments
Net Name Clock Assignment
CARRY Internal CLK1
CLKX External CLK0
CLK1X External CLK2
GLB and GLB Output Statistics
GLB Name, Location GLB Statistics GLB Output Statistics
GLB Output Name Ins, Outs, PTs Ins, FOs, PTs, Levels, PTSABP
glb00, D7 10, 4, 15
COUNT1[0] 5, 7, 3, 3, -
COUNT1[1] 7, 7, 5, 3, -
COUNT1[2] 6, 7, 4, 3, -
EN 3, 2, 3, 2, -
glb01, C0 5, 4, 4
AND_1072 2, 1, 1, 1, 1PT
AND_1073 2, 1, 1, 1, 1PT
AND_1074 2, 1, 1, 1, 1PT
CARRY 3, 6, 1, 1, 1PT
glb02, C3 10, 4, 6
AND_1075 2, 1, 1, 1, 1PT
DEF_1233 10, 1, 2, 1, -
STATE_C[1] 10, 4, 2, 1, -
UQNN_N6 4, 1, 1, 1, 1PT
glb03, D5 10, 4, 19
COUNT[0] 1, 3, 1, 1, 1PT
N_143_I 9, 1, 8, 1, -
N_148_I 9, 1, 8, 1, -
N_150_I 9, 1, 6, 1, -
glb04, A1 10, 4, 15
COUNT0[1] 5, 6, 3, 1, 4PT
N_145_I 9, 1, 6, 1, -
N_155_I 9, 1, 6, 1, -
VCC_1283 0, 1, 0, 0, -
glb05_part1, D6 9, 1, 8
OR_759 9, 1, 8, 1, -
glb05_part2, D1 10, 3, 9
LOAD 8, 3, 1, 1, 1PT
OR_763 9, 1, 6, 1, -
STATE[0] 9, 5, 2, 1, -
glb06, A6 2, 4, 4
AND_1068 2, 1, 1, 1, 1PT
AND_1069 2, 1, 1, 1, 1PT
AND_1070 2, 1, 1, 1, 1PT
AND_1071 2, 1, 1, 1, 1PT
glb07, A2 3, 2, 5
COUNT[1] 2, 2, 2, 1, 4PT
COUNT[2] 3, 2, 3, 1, 4PT
glb08, B3 2, 2, 3
COUNTA[0] 1, 6, 1, 1, 1PT
COUNTA[1] 2, 2, 2, 1, 4PT
glb09, D3 11, 4, 14
COUNT0[0] 2, 6, 1, 1, 1PT
COUNT0[2] 6, 6, 4, 1, 4PT
COUNT0[3] 5, 6, 4, 1, 4PT
COUNT1[3] 6, 7, 5, 3, -
glb11, A0 1, 1, 1
STATE_C[1]_buff1 1, 1, 1, 1, 1PT
glb12, B0 4, 4, 4
AND_1068_buff1 1, 1, 1, 2, 1PT
AND_1069_buff1 1, 1, 1, 2, 1PT
AND_1070_buff1 1, 1, 1, 2, 1PT
AND_1071_buff1 1, 1, 1, 2, 1PT
glb13, D0 3, 3, 3
N_145_I_buff1 1, 1, 1, 2, 1PT
N_155_I_buff1 1, 1, 1, 2, 1PT
VCC_1283_buff1 1, 1, 1, 1, 1PT
Maximum-Level Trace
GLB Level, Name, Ins GLB Output Name
3, glb00, 11 COUNT1[2]
2, glb00 EN
1, glb02 UQNN_N6
3, glb00, 12 COUNT1[1]
2, glb00 EN
1, glb02 UQNN_N6
3, glb00, 10 COUNT1[0]
2, glb00 EN
1, glb02 UQNN_N6
3, glb09, 11 COUNT1[3]
2, glb00 EN
1, glb02 UQNN_N6
Pin Assignments
Pin Name Pin Assignment Pin Type, Pin Attribute
SEGOUT(7) 3 Output, PULLUP
SEGOUT(6) 4 Output, PULLUP
SEGOUT(5) 5 Output, PULLUP
SEGOUT(4) 6 Output, PULLUP
SEGOUT(3) 7 Output, PULLUP
SEGOUT(2) 8 Output, PULLUP
SEGOUT(1) 9 Output, PULLUP
SEGOUT(0) 10 Output, PULLUP
CLK 20 Clock Input, PULLUP
SELOUT(3) 45 Output, PULLUP
SELOUT(2) 46 Output, PULLUP
SELOUT(1) 47 Output, PULLUP
SELOUT(0) 48 Output, PULLUP
CLK1 63 Clock Input, PULLUP
G2 78 Output, PULLUP
Y2 79 Output, PULLUP
R2 80 Output, PULLUP
G1 81 Output, PULLUP
Y1 82 Output, PULLUP
R1 83 Output, PULLUP
Design process management completed successfully
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