📄 trafic.rp-
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ispEXPERT Compiler Release 0.16.51, May 20 2002 13:06:40
Design Parameters
-----------------
EFFORT: MEDIUM (2)
IGNORE_FIXED_PIN: OFF
MAX_GLB_IN: 16
MAX_GLB_OUT: 4
OUTPUT_FORM: VERILOG, VHDL
OS_VERSION: Windows NT 5.0
PARAM_FILE: 'e:\edaprogram\pt1032e\trafic\ispxpert'
PIN_FILE: 'e:\edaprogram\pt1032e\trafic\trafic.xpn'
STRATEGY: DELAY
TIMING_ANALYZER: ON
USE_GLOBAL_RESET: ON
Design Specification
--------------------
Design: trafic
Part: ispLSI1032E-70LJ84
ISP: ON
ISP_EXCEPT_Y2: OFF
PULL: UP
SECURITY: OFF
SLOWSLEW: OFF
Number of Critical Pins: 0
Number of Free Pins: 0
Number of Locked Pins: 20
Number of Reserved Pins: 0
Input Pins
Pin Name Pin Attribute
CLK LOCK 20, PULLUP
CLK1 LOCK 63, PULLUP
Output Pins
Pin Name Pin Attribute
G1 LOCK 81, PULLUP
G2 LOCK 78, PULLUP
R1 LOCK 83, PULLUP
R2 LOCK 80, PULLUP
SEGOUT(0) LOCK 10, PULLUP
SEGOUT(1) LOCK 9, PULLUP
SEGOUT(2) LOCK 8, PULLUP
SEGOUT(3) LOCK 7, PULLUP
SEGOUT(4) LOCK 6, PULLUP
SEGOUT(5) LOCK 5, PULLUP
SEGOUT(6) LOCK 4, PULLUP
SEGOUT(7) LOCK 3, PULLUP
SELOUT(0) LOCK 48, PULLUP
SELOUT(1) LOCK 47, PULLUP
SELOUT(2) LOCK 46, PULLUP
SELOUT(3) LOCK 45, PULLUP
Y1 LOCK 82, PULLUP
Y2 LOCK 79, PULLUP
Hardmacro Instances
Instance Name Hardmacro Name
EN LD11
Pre-Route Design Statistics
---------------------------
Number of Macrocells: 36
Number of GLBs: 10
Number of I/Os: 18
Number of Nets: 35
Number of Free Inputs: 0
Number of Free Outputs: 0
Number of Free Three-States: 0
Number of Free Bidi's: 0
Number of Locked Input IOCs: 0
Number of Locked DIs: 0
Number of Locked Outputs: 18
Number of Locked Three-States: 0
Number of Locked Bidi's: 0
Number of CRIT Outputs: 0
Number of Global OEs: 0
Number of External Clocks: 2
GLB Utilization (Out of 32): 31%
I/O Utilization (Out of 68): 26%
Net Utilization (Out of 196): 17%
Nets with Fanout of 1: 18
Nets with Fanout of 2: 4
Nets with Fanout of 3: 2
Nets with Fanout of 4: 1
Nets with Fanout of 5: 6
Nets with Fanout of 6: 4
Average Fanout per Net: 2.57
GLBs with 2 Input(s): 2
GLBs with 3 Input(s): 1
GLBs with 5 Input(s): 1
GLBs with 10 Input(s): 5
GLBs with 11 Input(s): 1
Average Inputs per GLB: 7.30
GLBs with 2 Output(s): 2
GLBs with 4 Output(s): 8
Average Outputs per GLB: 3.60
Number of GLB Registers: 18
Number of IOC Registers: 0
Post-Route Design Implementation
--------------------------------
Number of Macrocells: 36
Number of GLBs: 14
Number of IOCs: 18
Number of DIs: 0
Number of GLB Levels: 3
GLB glb00, D7
10 Input(s)
(glb01.O0, CARRY, I15), (glb00.O0, COUNT1[0], I16), (glb00.O2,
COUNT1[1], I5), (glb00.O3, COUNT1[2], I4), (glb09.O3,
COUNT1[3], I0), (glb00.O1, EN, I17), (glb05_part2.O0,
LOAD, I11), (glb05_part2.O3, STATE[0], I8), (glb11.O1,
STATE_C[1]_buff1, I14), (glb02.O1, UQNN_N6, I6)
4 Output(s)
(EN, O1), (COUNT1[2], O3), (COUNT1[1], O2), (COUNT1[0], O0)
15 Product Term(s)
Output EN
3 Input(s)
EN, UQNN_N6, CARRY
2 Fanout(s)
glb09.I6, glb00.I17
3 Product Term(s)
2 GLB Level(s)
EN = (CARRY & EN
# EN & UQNN_N6
# UQNN_N6 & !CARRY)
Output COUNT1[2]
6 Input(s)
EN, LOAD, COUNT1[2], COUNT1[0], COUNT1[3], COUNT1[1]
7 Fanout(s)
glb04.I11, glb02.I4, glb05_part2.I4, glb09.I4, glb03.I4,
glb05_part1.I4, glb00.I4
4 Product Term(s)
3 GLB Level(s)
COUNT1[2].D = (COUNT1[2] & !EN
# COUNT1[0] & COUNT1[2] & !LOAD
# COUNT1[1] & COUNT1[2] & !LOAD
# COUNT1[3] & EN & !COUNT1[0] & !COUNT1[1] & !COUNT1[2]
& !LOAD)
COUNT1[2].C = CARRY
COUNT1[2].R =
Output COUNT1[1]
7 Input(s)
EN, LOAD, COUNT1[2], STATE[0], COUNT1[0], COUNT1[3],
COUNT1[1]
7 Fanout(s)
glb04.I14, glb02.I1, glb05_part2.I1, glb09.I1, glb03.I1,
glb05_part1.I1, glb00.I5
5 Product Term(s)
3 GLB Level(s)
COUNT1[1].D = (COUNT1[1] & !EN
# COUNT1[0] & COUNT1[1] & !LOAD
# EN & LOAD & STATE[0]
# COUNT1[2] & EN & !COUNT1[0] & !COUNT1[1] & !LOAD
# COUNT1[3] & EN & !COUNT1[0] & !COUNT1[1] & !LOAD)
COUNT1[1].C = CARRY
COUNT1[1].R =
Output COUNT1[0]
5 Input(s)
EN, LOAD, STATE[0], COUNT1[0], STATE_C[1]_buff1
7 Fanout(s)
glb04.I12, glb02.I3, glb05_part2.I3, glb09.I7, glb03.I3,
glb05_part1.I3, glb00.I16
3 Product Term(s)
3 GLB Level(s)
COUNT1[0].D = (COUNT1[0] & !EN
# EN & !COUNT1[0] & !LOAD
# EN & LOAD & STATE[0] & STATE_C[1]_buff1)
COUNT1[0].C = CARRY
COUNT1[0].R =
Clock GLB glb01, C0
5 Input(s)
(glb03.O1, COUNT[0], I10), (glb07.O1, COUNT[1], I13),
(glb07.O0, COUNT[2], I12), (glb05_part2.O3, STATE[0], I8),
(glb02.O3, STATE_C[1], I4)
4 Output(s)
(CARRY, O0), (AND_1074, O2), (AND_1073, O3), (AND_1072, O1)
4 Product Term(s)
Output CARRY
3 Input(s)
COUNT[0], COUNT[1], COUNT[2]
6 Fanout(s)
glb04.CLK1, glb02.CLK1, glb05_part2.CLK1, glb09.CLK1,
glb00.I15, glb00.CLK1
1 Product Term(s)
1 GLB Level(s)
CARRY.D = COUNT[0] & COUNT[1] & COUNT[2]
CARRY.C = CLKX
CARRY.R =
Output AND_1074
2 Input(s)
STATE_C[1], STATE[0]
1 Fanout(s)
G2.IR
1 Product Term(s)
1 GLB Level(s)
AND_1074 = STATE[0] & !STATE_C[1]
Output AND_1073
2 Input(s)
STATE_C[1], STATE[0]
1 Fanout(s)
Y2.IR
1 Product Term(s)
1 GLB Level(s)
AND_1073 = !STATE_C[1] & !STATE[0]
Output AND_1072
2 Input(s)
STATE_C[1], STATE[0]
1 Fanout(s)
G1.IR
1 Product Term(s)
1 GLB Level(s)
AND_1072 = STATE[0] & STATE_C[1]
GLB glb02, C3
10 Input(s)
(glb09.O1, COUNT0[0], I6), (glb04.O2, COUNT0[1], I9),
(glb09.O0, COUNT0[2], I7), (glb09.O2, COUNT0[3], I5),
(glb00.O0, COUNT1[0], I3), (glb00.O2, COUNT1[1], I1),
(glb00.O3, COUNT1[2], I4), (glb09.O3, COUNT1[3], I0),
(glb05_part2.O3, STATE[0], I8), (glb02.O3, STATE_C[1], I17)
4 Output(s)
(UQNN_N6, O1), (STATE_C[1], O3), (DEF_1233, O0),
(AND_1075, O2)
6 Product Term(s)
Output UQNN_N6
4 Input(s)
COUNT0[1], COUNT0[2], COUNT0[0], COUNT0[3]
1 Fanout(s)
glb00.I6
1 Product Term(s)
1 GLB Level(s)
UQNN_N6 = !COUNT0[0] & !COUNT0[1] & !COUNT0[2] & !COUNT0[3]
Output STATE_C[1]
10 Input(s)
COUNT0[1], STATE_C[1], COUNT1[2], STATE[0], COUNT0[2],
COUNT1[0], COUNT1[3], COUNT0[0], COUNT0[3], COUNT1[1]
4 Fanout(s)
glb11.I15, glb01.I4, glb02.I17, R1.IR
2 Product Term(s)
1 GLB Level(s)
STATE_C[1].D = (STATE_C[1])
$ !COUNT0[0] & !COUNT0[1] & !COUNT0[2] & !COUNT0[3]
& !COUNT1[0] & !COUNT1[1] & !COUNT1[2] & !COUNT1[3]
& !STATE[0]
!STATE_C[1].C = CARRY
STATE_C[1].R =
Output DEF_1233
10 Input(s)
COUNT0[1], STATE_C[1], COUNT1[2], STATE[0], COUNT0[2],
COUNT1[0], COUNT1[3], COUNT0[0], COUNT0[3], COUNT1[1]
1 Fanout(s)
R2.IR
2 Product Term(s)
1 GLB Level(s)
DEF_1233.D = (STATE_C[1])
$ !COUNT0[0] & !COUNT0[1] & !COUNT0[2] & !COUNT0[3]
& !COUNT1[0] & !COUNT1[1] & !COUNT1[2] & !COUNT1[3]
& !STATE[0]
!DEF_1233.C = CARRY
DEF_1233.R =
Output AND_1075
2 Input(s)
STATE_C[1], STATE[0]
1 Fanout(s)
Y1.IR
1 Product Term(s)
1 GLB Level(s)
AND_1075 = STATE_C[1] & !STATE[0]
GLB glb03, D5
10 Input(s)
(glb09.O1, COUNT0[0], I6), (glb04.O2, COUNT0[1], I9),
(glb09.O0, COUNT0[2], I7), (glb09.O2, COUNT0[3], I5),
(glb00.O0, COUNT1[0], I3), (glb00.O2, COUNT1[1], I1),
(glb00.O3, COUNT1[2], I4), (glb09.O3, COUNT1[3], I0),
(glb08.O1, COUNTA[0], I2), (glb03.O1, COUNT[0], I16)
4 Output(s)
(N_150_I, O2), (N_148_I, O3), (N_143_I, O0), (COUNT[0], O1)
19 Product Term(s)
Output N_150_I
9 Input(s)
COUNTA[0], COUNT0[1], COUNT1[2], COUNT0[2], COUNT1[0],
COUNT1[3], COUNT0[0], COUNT0[3], COUNT1[1]
1 Fanout(s)
SEGOUT(5).IR
6 Product Term(s)
1 GLB Level(s)
N_150_I = (COUNT1[1] & COUNT1[2] & COUNT1[3] & COUNTA[0]
# COUNT0[1] & COUNT0[2] & COUNT0[3] & !COUNTA[0]
# COUNT0[2] & COUNT0[3] & !COUNTA[0] & !COUNT0[0]
# COUNT1[2] & COUNT1[3] & COUNTA[0] & !COUNT1[0]
# COUNT0[1] & !COUNTA[0] & !COUNT0[0] & !COUNT0[2]
& !COUNT0[3]
# COUNT1[1] & COUNTA[0] & !COUNT1[0] & !COUNT1[2]
& !COUNT1[3])
Output N_148_I
9 Input(s)
COUNTA[0], COUNT0[1], COUNT1[2], COUNT0[2], COUNT1[0],
COUNT1[3], COUNT0[0], COUNT0[3], COUNT1[1]
1 Fanout(s)
SEGOUT(4).IR
8 Product Term(s)
1 GLB Level(s)
N_148_I = (COUNT1[0] & COUNT1[1] & COUNT1[2] & COUNTA[0]
# COUNT0[0] & COUNT0[1] & COUNT0[2] & !COUNTA[0]
# COUNT1[1] & COUNT1[3] & COUNTA[0] & !COUNT1[0] & !COUNT1[2]
# COUNT0[1] & COUNT0[3] & !COUNTA[0] & !COUNT0[0]
& !COUNT0[2]
# COUNT1[2] & COUNTA[0] & !COUNT1[0] & !COUNT1[1]
& !COUNT1[3]
# COUNT1[0] & COUNTA[0] & !COUNT1[1] & !COUNT1[2]
& !COUNT1[3]
# COUNT0[2] & !COUNTA[0] & !COUNT0[0] & !COUNT0[1]
& !COUNT0[3]
# COUNT0[0] & !COUNTA[0] & !COUNT0[1] & !COUNT0[2]
& !COUNT0[3])
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