trafic.laf

来自「CPLD lattice1032 VHDL实现交通灯控制！」· LAF 代码 · 共 1,422 行 · 第 1/3 页

 END;
 SYM AND2 num_and4_1[6];
   PIN Z0 OUT N_115;
   PIN A0 IN N_97_I_0;
   PIN A1 IN N_118;
 END;
 SYM AND2 num_31;
   PIN Z0 OUT NUM_C[1];
   PIN A0 IN N_80_I;
   PIN A1 IN N_141_I;
 END;
 SYM AND2 UQBN_B5;
   PIN Z0 OUT COUNT_C1;
   PIN A0 IN COUNT[0];
   PIN A1 IN COUNT[1];
 END;
 SYM AND2 UQBN_B4;
   PIN Z0 OUT UQNN_N1;
   PIN A0 IN COUNT[2];
   PIN A1 IN COUNT_C1;
 END;
 SYM XOR2 count_n1;
   PIN Z0 OUT COUNT_N1;
   PIN A0 IN COUNT[0];
   PIN A1 IN COUNT[1];
 END;
 SYM XOR2 count_n2;
   PIN Z0 OUT COUNT_N2;
   PIN A0 IN COUNT[2];
   PIN A1 IN COUNT_C1;
 END;
 SYM XOR2 num_85;
   PIN Z0 OUT N_96;
   PIN A0 IN temp[2]_Z0;
   PIN A1 IN TEMP_I[0];
 END;
 SYM AND2 UQBN_B2;
   PIN Z0 OUT UQNN_N2;
   PIN A0 IN STATE[0];
   PIN A1 IN STATE_C[1];
 END;
 SYM AND2 num_82;
   PIN Z0 OUT N_118;
   PIN A0 IN temp[0]_Z0;
   PIN A1 IN temp[2]_Z0;
 END;
 SYM AND2 num_83;
   PIN Z0 OUT N_119;
   PIN A0 IN temp[3]_Z0;
   PIN A1 IN TEMP_I[0];
 END;
 SYM AND2 num_84;
   PIN Z0 OUT N_120;
   PIN A0 IN N_119;
   PIN A1 IN temp[2]_Z0;
 END;
 SYM AND2 num_86;
   PIN Z0 OUT N_97_I_0;
   PIN A0 IN TEMP_I[1];
   PIN A1 IN TEMP_I[3];
 END;
 SYM AND2 num_87;
   PIN Z0 OUT N_98_I_0;
   PIN A0 IN temp[1]_Z0;
   PIN A1 IN TEMP_I[2];
 END;
 SYM AND2 num_and4[1];
   PIN Z0 OUT N_102;
   PIN A0 IN N_118;
   PIN A1 IN temp[1]_Z0;
 END;
 SYM AND2 num_and4_0[1];
   PIN Z0 OUT N_103;
   PIN A0 IN N_97_I_0;
   PIN A1 IN TEMP_I[2];
 END;
 SYM AND2 num_and4_1[1];
   PIN Z0 OUT N_104;
   PIN A0 IN N_120;
   PIN A1 IN TEMP_I[1];
 END;
 SYM AND2 num_i_and4[2];
   PIN Z0 OUT N_105;
   PIN A0 IN N_98_I_0_I;
   PIN A1 IN TEMP_I[0];
 END;
 SYM AND2 num_i_and4_0[2];
   PIN Z0 OUT N_106;
   PIN A0 IN temp[3]_Z0;
   PIN A1 IN TEMP_I[2];
 END;
 SYM AND2 num_i_and4_1[2];
   PIN Z0 OUT N_107;
   PIN A0 IN N_97_I_0;
   PIN A1 IN temp[2]_Z0;
 END;
 SYM AND2 num_and4[3];
   PIN Z0 OUT N_108;
   PIN A0 IN temp[0]_Z0;
   PIN A1 IN TEMP_I[3];
 END;
 SYM LD11 en HARD ;
   PIN Q0 OUT EN;
   PIN D0 IN UQNN_N6;
   PIN G IN CARRY_I;
 END;
 SYM XINPUT clk_$1I45;
   PIN Z0 OUT clk_Z0;
   PIN XI0 IN CLK;
 END;
 SYM XINPUT clk1_$1I45;
   PIN Z0 OUT clk1_Z0;
   PIN XI0 IN CLK1;
 END;
 SYM XOUTPUT R1_$1I42;
   PIN XO0 OUT R1_XO0;
   PIN A0 IN STATE_C[1];
 END;
 SYM XOUTPUT R2_$1I42;
   PIN XO0 OUT R2_XO0;
   PIN A0 IN STATE_C_I[1];
 END;
 SYM XOUTPUT Y1_$1I42;
   PIN XO0 OUT Y1_XO0;
   PIN A0 IN UQNN_N15;
 END;
 SYM XOUTPUT Y2_$1I42;
   PIN XO0 OUT Y2_XO0;
   PIN A0 IN UQNN_N14;
 END;
 SYM XOUTPUT G1_$1I42;
   PIN XO0 OUT G1_XO0;
   PIN A0 IN UQNN_N13;
 END;
 SYM XOUTPUT G2_$1I42;
   PIN XO0 OUT G2_XO0;
   PIN A0 IN UQNN_N12;
 END;
 SYM XOUTPUT segout[0]_$1I42;
   PIN XO0 OUT segout[0]_XO0;
   PIN A0 IN VCC;
 END;
 SYM XOUTPUT segout[1]_$1I42;
   PIN XO0 OUT segout[1]_XO0;
   PIN A0 IN NUM_C[1];
 END;
 SYM XOUTPUT segout[2]_$1I42;
   PIN XO0 OUT segout[2]_XO0;
   PIN A0 IN NUM_C[2];
 END;
 SYM XOUTPUT segout[3]_$1I42;
   PIN XO0 OUT segout[3]_XO0;
   PIN A0 IN N_155_I;
 END;
 SYM XOUTPUT segout[4]_$1I42;
   PIN XO0 OUT segout[4]_XO0;
   PIN A0 IN N_148_I;
 END;
 SYM XOUTPUT segout[5]_$1I42;
   PIN XO0 OUT segout[5]_XO0;
   PIN A0 IN N_150_I;
 END;
 SYM XOUTPUT segout[6]_$1I42;
   PIN XO0 OUT segout[6]_XO0;
   PIN A0 IN N_145_I;
 END;
 SYM XOUTPUT segout[7]_$1I42;
   PIN XO0 OUT segout[7]_XO0;
   PIN A0 IN N_143_I;
 END;
 SYM XOUTPUT selout[0]_$1I42;
   PIN XO0 OUT selout[0]_XO0;
   PIN A0 IN UN1_SEL_I;
 END;
 SYM XOUTPUT selout[1]_$1I42;
   PIN XO0 OUT selout[1]_XO0;
   PIN A0 IN UN3_SEL_I;
 END;
 SYM XOUTPUT selout[2]_$1I42;
   PIN XO0 OUT selout[2]_XO0;
   PIN A0 IN UN9_SEL_I;
 END;
 SYM XOUTPUT selout[3]_$1I42;
   PIN XO0 OUT selout[3]_XO0;
   PIN A0 IN UN1_COUNTA_I;
 END;
 SYM INV temp[3]_$1I38;
   PIN ZN0 OUT temp[3]_$1N22;
   PIN A0 IN COUNTA[0];
 END;
 SYM OR2 temp[3]_$1I35;
   PIN Z0 OUT temp[3]_Z0;
   PIN A0 IN temp[3]_$1N6;
   PIN A1 IN temp[3]_$1N8;
 END;
 SYM AND2 temp[3]_$1I31;
   PIN Z0 OUT temp[3]_$1N8;
   PIN A0 IN COUNT1[3];
   PIN A1 IN COUNTA[0];
 END;
 SYM AND2 temp[3]_$1I25;
   PIN Z0 OUT temp[3]_$1N6;
   PIN A0 IN COUNT0[3];
   PIN A1 IN temp[3]_$1N22;
 END;
 SYM INV temp[2]_$1I38;
   PIN ZN0 OUT temp[2]_$1N22;
   PIN A0 IN COUNTA[0];
 END;
 SYM OR2 temp[2]_$1I35;
   PIN Z0 OUT temp[2]_Z0;
   PIN A0 IN temp[2]_$1N6;
   PIN A1 IN temp[2]_$1N8;
 END;
 SYM AND2 temp[2]_$1I31;
   PIN Z0 OUT temp[2]_$1N8;
   PIN A0 IN COUNT1[2];
   PIN A1 IN COUNTA[0];
 END;
 SYM AND2 temp[2]_$1I25;
   PIN Z0 OUT temp[2]_$1N6;
   PIN A0 IN COUNT0[2];
   PIN A1 IN temp[2]_$1N22;
 END;
 SYM INV temp[1]_$1I38;
   PIN ZN0 OUT temp[1]_$1N22;
   PIN A0 IN COUNTA[0];
 END;
 SYM OR2 temp[1]_$1I35;
   PIN Z0 OUT temp[1]_Z0;
   PIN A0 IN temp[1]_$1N6;
   PIN A1 IN temp[1]_$1N8;
 END;
 SYM AND2 temp[1]_$1I31;
   PIN Z0 OUT temp[1]_$1N8;
   PIN A0 IN COUNT1[1];
   PIN A1 IN COUNTA[0];
 END;
 SYM AND2 temp[1]_$1I25;
   PIN Z0 OUT temp[1]_$1N6;
   PIN A0 IN COUNT0[1];
   PIN A1 IN temp[1]_$1N22;
 END;
 SYM INV temp[0]_$1I38;
   PIN ZN0 OUT temp[0]_$1N22;
   PIN A0 IN COUNTA[0];
 END;
 SYM OR2 temp[0]_$1I35;
   PIN Z0 OUT temp[0]_Z0;
   PIN A0 IN temp[0]_$1N6;
   PIN A1 IN temp[0]_$1N8;
 END;
 SYM AND2 temp[0]_$1I31;
   PIN Z0 OUT temp[0]_$1N8;
   PIN A0 IN COUNT1[0];
   PIN A1 IN COUNTA[0];
 END;
 SYM AND2 temp[0]_$1I25;
   PIN Z0 OUT temp[0]_$1N6;
   PIN A0 IN COUNT0[0];
   PIN A1 IN temp[0]_$1N22;
 END;
 SYM INV _9_$1I38;
   PIN ZN0 OUT _9_$1N22;
   PIN A0 IN UQNN_N11;
 END;
 SYM OR2 _9_$1I35;
   PIN Z0 OUT _9_Z0;
   PIN A0 IN _9_$1N6;
   PIN A1 IN _9_$1N8;
 END;
 SYM AND2 _9_$1I31;
   PIN Z0 OUT _9_$1N8;
   PIN A0 IN COUNT0[3];
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 _9_$1I25;
   PIN Z0 OUT _9_$1N6;
   PIN A0 IN LOAD_I;
   PIN A1 IN _9_$1N22;
 END;
 SYM INV _7_$1I38;
   PIN ZN0 OUT _7_$1N22;
   PIN A0 IN UQNN_N11;
 END;
 SYM OR2 _7_$1I35;
   PIN Z0 OUT _7_Z0;
   PIN A0 IN _7_$1N6;
   PIN A1 IN _7_$1N8;
 END;
 SYM AND2 _7_$1I31;
   PIN Z0 OUT _7_$1N8;
   PIN A0 IN COUNT0[2];
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 _7_$1I25;
   PIN Z0 OUT _7_$1N6;
   PIN A0 IN UN1_LOAD_1;
   PIN A1 IN _7_$1N22;
 END;
 SYM INV _3_$1I38;
   PIN ZN0 OUT _3_$1N22;
   PIN A0 IN UQNN_N11;
 END;
 SYM OR2 _3_$1I35;
   PIN Z0 OUT _3_Z0;
   PIN A0 IN _3_$1N6;
   PIN A1 IN _3_$1N8;
 END;
 SYM AND2 _3_$1I31;
   PIN Z0 OUT _3_$1N8;
   PIN A0 IN COUNT0[0];
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 _3_$1I25;
   PIN Z0 OUT _3_$1N6;
   PIN A0 IN LOAD_I;
   PIN A1 IN _3_$1N22;
 END;
 SYM INV count1_e3_$1I38;
   PIN ZN0 OUT count1_e3_$1N22;
   PIN A0 IN EN;
 END;
 SYM OR2 count1_e3_$1I35;
   PIN Z0 OUT count1_e3_Z0;
   PIN A0 IN count1_e3_$1N6;
   PIN A1 IN count1_e3_$1N8;
 END;
 SYM AND2 count1_e3_$1I31;
   PIN Z0 OUT count1_e3_$1N8;
   PIN A0 IN COUNT1_N3;
   PIN A1 IN EN;
 END;
 SYM AND2 count1_e3_$1I25;
   PIN Z0 OUT count1_e3_$1N6;
   PIN A0 IN COUNT1[3];
   PIN A1 IN count1_e3_$1N22;
 END;
 SYM INV state_0[1]_$1I38;
   PIN ZN0 OUT state_0[1]_$1N22;
   PIN A0 IN UQNN_N7;
 END;
 SYM OR2 state_0[1]_$1I35;
   PIN Z0 OUT state_0[1]_Z0;
   PIN A0 IN state_0[1]_$1N6;
   PIN A1 IN state_0[1]_$1N8;
 END;
 SYM AND2 state_0[1]_$1I31;
   PIN Z0 OUT state_0[1]_$1N8;
   PIN A0 IN NEXT_STATE[1];
   PIN A1 IN UQNN_N7;
 END;
 SYM AND2 state_0[1]_$1I25;
   PIN Z0 OUT state_0[1]_$1N6;
   PIN A0 IN STATE_C[1];
   PIN A1 IN state_0[1]_$1N22;
 END;
 SYM INV _11_$1I38;
   PIN ZN0 OUT _11_$1N22;
   PIN A0 IN N_19_I;
 END;
 SYM OR2 _11_$1I35;
   PIN Z0 OUT _11_Z0;
   PIN A0 IN _11_$1N6;
   PIN A1 IN _11_$1N8;
 END;
 SYM AND2 _11_$1I31;
   PIN Z0 OUT _11_$1N8;
   PIN A0 IN COUNT1[0];
   PIN A1 IN N_19_I;
 END;
 SYM AND2 _11_$1I25;
   PIN Z0 OUT _11_$1N6;
   PIN A0 IN N_38_I;
   PIN A1 IN _11_$1N22;
 END;
 SYM INV count1_e0_$1I38;
   PIN ZN0 OUT count1_e0_$1N22;
   PIN A0 IN EN;
 END;
 SYM OR2 count1_e0_$1I35;
   PIN Z0 OUT count1_e0_Z0;
   PIN A0 IN count1_e0_$1N6;
   PIN A1 IN count1_e0_$1N8;
 END;
 SYM AND2 count1_e0_$1I31;
   PIN Z0 OUT count1_e0_$1N8;
   PIN A0 IN COUNT1_N0;
   PIN A1 IN EN;
 END;
 SYM AND2 count1_e0_$1I25;
   PIN Z0 OUT count1_e0_$1N6;
   PIN A0 IN COUNT1[0];
   PIN A1 IN count1_e0_$1N22;
 END;
 SYM INV _13_$1I38;
   PIN ZN0 OUT _13_$1N22;
   PIN A0 IN N_19_I;
 END;
 SYM OR2 _13_$1I35;
   PIN Z0 OUT _13_Z0;
   PIN A0 IN _13_$1N6;
   PIN A1 IN _13_$1N8;
 END;
 SYM AND2 _13_$1I31;
   PIN Z0 OUT _13_$1N8;
   PIN A0 IN COUNT1[1];
   PIN A1 IN N_19_I;
 END;
 SYM AND2 _13_$1I25;
   PIN Z0 OUT _13_$1N6;
   PIN A0 IN UN1_LOAD_3;
   PIN A1 IN _13_$1N22;
 END;
 SYM INV count1_e1_$1I38;
   PIN ZN0 OUT count1_e1_$1N22;
   PIN A0 IN EN;
 END;
 SYM OR2 count1_e1_$1I35;
   PIN Z0 OUT count1_e1_Z0;
   PIN A0 IN count1_e1_$1N6;
   PIN A1 IN count1_e1_$1N8;
 END;
 SYM AND2 count1_e1_$1I31;
   PIN Z0 OUT count1_e1_$1N8;
   PIN A0 IN COUNT1_N1;
   PIN A1 IN EN;
 END;
 SYM AND2 count1_e1_$1I25;
   PIN Z0 OUT count1_e1_$1N6;
   PIN A0 IN COUNT1[1];
   PIN A1 IN count1_e1_$1N22;
 END;
 SYM INV count1_e2_$1I38;
   PIN ZN0 OUT count1_e2_$1N22;
   PIN A0 IN EN;
 END;
 SYM OR2 count1_e2_$1I35;
   PIN Z0 OUT count1_e2_Z0;
   PIN A0 IN count1_e2_$1N6;
   PIN A1 IN count1_e2_$1N8;
 END;
 SYM AND2 count1_e2_$1I31;
   PIN Z0 OUT count1_e2_$1N8;
   PIN A0 IN COUNT1_N2;
   PIN A1 IN EN;
 END;
 SYM AND2 count1_e2_$1I25;
   PIN Z0 OUT count1_e2_$1N6;
   PIN A0 IN COUNT1[2];
   PIN A1 IN count1_e2_$1N22;
 END;
 SYM INV _17_$1I38;
   PIN ZN0 OUT _17_$1N22;
   PIN A0 IN N_19_I;
 END;
 SYM OR2 _17_$1I35;
   PIN Z0 OUT _17_Z0;
   PIN A0 IN _17_$1N6;
   PIN A1 IN _17_$1N8;
 END;
 SYM AND2 _17_$1I31;
   PIN Z0 OUT _17_$1N8;
   PIN A0 IN COUNT1[3];
   PIN A1 IN N_19_I;
 END;
 SYM AND2 _17_$1I25;
   PIN Z0 OUT _17_$1N6;
   PIN A0 IN LOAD_I;
   PIN A1 IN _17_$1N22;
 END;
END ;
END ;