trafic.laf

来自「CPLD lattice1032 VHDL实现交通灯控制！」· LAF 代码 · 共 1,422 行 · 第 1/3 页

   PIN A0 IN temp[2]_Z0;
 END;
 SYM INV count1_i[2];
   PIN ZN0 OUT COUNT1_I[2];
   PIN A0 IN COUNT1[2];
 END;
 SYM INV count0_i[3];
   PIN ZN0 OUT COUNT0_I[3];
   PIN A0 IN COUNT0[3];
 END;
 SYM INV count0_i[2];
   PIN ZN0 OUT COUNT0_I[2];
   PIN A0 IN COUNT0[2];
 END;
 SYM INV count1_i[3];
   PIN ZN0 OUT COUNT1_I[3];
   PIN A0 IN COUNT1[3];
 END;
 SYM INV N_104_i;
   PIN ZN0 OUT N_104_I;
   PIN A0 IN N_104;
 END;
 SYM INV N_110_i;
   PIN ZN0 OUT N_110_I;
   PIN A0 IN N_110;
 END;
 SYM INV N_97_i_0_i;
   PIN ZN0 OUT N_97_I_0_I;
   PIN A0 IN N_97_I_0;
 END;
 SYM INV un1_counta_i;
   PIN ZN0 OUT UN1_COUNTA_I;
   PIN A0 IN UN1_COUNTA;
 END;
 SYM INV un9_sel_i;
   PIN ZN0 OUT UN9_SEL_I;
   PIN A0 IN UN9_SEL;
 END;
 SYM INV un3_sel_i;
   PIN ZN0 OUT UN3_SEL_I;
   PIN A0 IN UN3_SEL;
 END;
 SYM INV un1_sel_i;
   PIN ZN0 OUT UN1_SEL_I;
   PIN A0 IN UN1_SEL;
 END;
 SYM INV N_143_i;
   PIN ZN0 OUT N_143_I;
   PIN A0 IN N_143;
 END;
 SYM INV N_145_i;
   PIN ZN0 OUT N_145_I;
   PIN A0 IN N_145;
 END;
 SYM INV N_150_i;
   PIN ZN0 OUT N_150_I;
   PIN A0 IN N_150;
 END;
 SYM INV N_107_i;
   PIN ZN0 OUT N_107_I;
   PIN A0 IN N_107;
 END;
 SYM INV N_106_i;
   PIN ZN0 OUT N_106_I;
   PIN A0 IN N_106;
 END;
 SYM INV N_105_i;
   PIN ZN0 OUT N_105_I;
   PIN A0 IN N_105;
 END;
 SYM INV N_120_i;
   PIN ZN0 OUT N_120_I;
   PIN A0 IN N_120;
 END;
 SYM INV N_112_i;
   PIN ZN0 OUT N_112_I;
   PIN A0 IN N_112;
 END;
 SYM INV N_111_i;
   PIN ZN0 OUT N_111_I;
   PIN A0 IN N_111;
 END;
 SYM INV N_102_i;
   PIN ZN0 OUT N_102_I;
   PIN A0 IN N_102;
 END;
 SYM INV N_103_i;
   PIN ZN0 OUT N_103_I;
   PIN A0 IN N_103;
 END;
 SYM INV N_116_i;
   PIN ZN0 OUT N_116_I;
   PIN A0 IN N_116;
 END;
 SYM INV N_114_i;
   PIN ZN0 OUT N_114_I;
   PIN A0 IN N_114;
 END;
 SYM INV N_115_i;
   PIN ZN0 OUT N_115_I;
   PIN A0 IN N_115;
 END;
 SYM INV N_113_i;
   PIN ZN0 OUT N_113_I;
   PIN A0 IN N_113;
 END;
 SYM INV temp_i[3];
   PIN ZN0 OUT TEMP_I[3];
   PIN A0 IN temp[3]_Z0;
 END;
 SYM INV temp_i[0];
   PIN ZN0 OUT TEMP_I[0];
   PIN A0 IN temp[0]_Z0;
 END;
 SYM INV temp_i[1];
   PIN ZN0 OUT TEMP_I[1];
   PIN A0 IN temp[1]_Z0;
 END;
 SYM AND2 num_and4_0_6_125;
   PIN Z0 OUT N_182;
   PIN A0 IN temp[3]_Z0;
   PIN A1 IN temp[0]_Z0;
 END;
 SYM AND2 num_and4_7_126;
   PIN Z0 OUT N_183;
   PIN A0 IN TEMP_I[1];
   PIN A1 IN temp[3]_Z0;
 END;
 SYM AND2 num_and4_5_127;
   PIN Z0 OUT N_184;
   PIN A0 IN TEMP_I[3];
   PIN A1 IN TEMP_I[0];
 END;
 SYM AND2 num_36_128;
   PIN Z0 OUT N_185;
   PIN A0 IN N_113_I;
   PIN A1 IN N_80_I;
 END;
 SYM AND2 num_36_129;
   PIN Z0 OUT N_186;
   PIN A0 IN N_115_I;
   PIN A1 IN N_114_I;
 END;
 SYM AND2 num_7_130;
   PIN Z0 OUT N_187;
   PIN A0 IN N_116_I;
   PIN A1 IN N_114_I;
 END;
 SYM AND2 num_1_131;
   PIN Z0 OUT N_188;
   PIN A0 IN N_103_I;
   PIN A1 IN N_102_I;
 END;
 SYM AND2 num_34_132;
   PIN Z0 OUT N_189;
   PIN A0 IN N_111_I;
   PIN A1 IN N_102_I;
 END;
 SYM AND2 num_35_133;
   PIN Z0 OUT N_190;
   PIN A0 IN N_120_I;
   PIN A1 IN N_112_I;
 END;
 SYM AND2 num_32_134;
   PIN Z0 OUT N_191;
   PIN A0 IN N_106_I;
   PIN A1 IN N_105_I;
 END;
 SYM AND2 num_32_135;
   PIN Z0 OUT N_192;
   PIN A0 IN N_80_I;
   PIN A1 IN N_107_I;
 END;
 SYM AND2 num_3_136;
   PIN Z0 OUT N_193;
   PIN A0 IN N_108_I;
   PIN A1 IN N_109_I;
 END;
 SYM INV N_108_i;
   PIN ZN0 OUT N_108_I;
   PIN A0 IN N_108;
 END;
 SYM INV N_109_i;
   PIN ZN0 OUT N_109_I;
   PIN A0 IN N_109;
 END;
 SYM INV N_80_i;
   PIN ZN0 OUT N_80_I;
   PIN A0 IN N_80;
 END;
 SYM AND2 num_36;
   PIN Z0 OUT N_145;
   PIN A0 IN N_185;
   PIN A1 IN N_186;
 END;
 SYM AND2 num[7];
   PIN Z0 OUT N_143;
   PIN A0 IN N_110_I;
   PIN A1 IN N_187;
 END;
 SYM AND2 num_and4_0[3];
   PIN Z0 OUT N_109;
   PIN A0 IN TEMP_I[1];
   PIN A1 IN N_181;
 END;
 SYM AND2 num_38_i_and2;
   PIN Z0 OUT N_80;
   PIN A0 IN N_179;
   PIN A1 IN N_180;
 END;
 SYM AND2 num[1];
   PIN Z0 OUT N_141;
   PIN A0 IN N_104_I;
   PIN A1 IN N_188;
 END;
 SYM AND2 _16;
   PIN Z0 OUT N_25_I_0;
   PIN A0 IN N_19_I;
   PIN A1 IN N_177;
 END;
 SYM AND2 UQBN_B12;
   PIN Z0 OUT UQNN_N6;
   PIN A0 IN UQNN_N8;
   PIN A1 IN N_176;
 END;
 SYM AND2 UQBN_B17;
   PIN Z0 OUT UQNN_N10;
   PIN A0 IN UQNN_N9;
   PIN A1 IN N_175;
 END;
 SYM AND2 UQBN_B22;
   PIN Z0 OUT N_175;
   PIN A0 IN COUNT1_I[3];
   PIN A1 IN COUNT1_I[2];
 END;
 SYM AND2 UQBN_B23;
   PIN Z0 OUT N_176;
   PIN A0 IN COUNT0_I[3];
   PIN A1 IN COUNT0_I[2];
 END;
 SYM AND2 _16_120;
   PIN Z0 OUT N_177;
   PIN A0 IN COUNT1_I[2];
   PIN A1 IN UQNN_N9;
 END;
 SYM AND2 num_and4_6_121;
   PIN Z0 OUT N_178;
   PIN A0 IN TEMP_I[0];
   PIN A1 IN temp[2]_Z0;
 END;
 SYM AND2 num_38_i_and2_122;
   PIN Z0 OUT N_179;
   PIN A0 IN temp[1]_Z0;
   PIN A1 IN temp[0]_Z0;
 END;
 SYM AND2 num_38_i_and2_123;
   PIN Z0 OUT N_180;
   PIN A0 IN temp[3]_Z0;
   PIN A1 IN temp[2]_Z0;
 END;
 SYM AND2 num_and4_0_3_124;
   PIN Z0 OUT N_181;
   PIN A0 IN temp[0]_Z0;
   PIN A1 IN TEMP_I[2];
 END;
 SYM AND2 num[3];
   PIN Z0 OUT N_155;
   PIN A0 IN N_107_I;
   PIN A1 IN N_193;
 END;
 SYM AND2 num_32;
   PIN Z0 OUT NUM_C[2];
   PIN A0 IN N_191;
   PIN A1 IN N_192;
 END;
 SYM AND2 num_35;
   PIN Z0 OUT N_150;
   PIN A0 IN N_80_I;
   PIN A1 IN N_190;
 END;
 SYM AND2 num_34;
   PIN Z0 OUT N_148;
   PIN A0 IN N_110_I;
   PIN A1 IN N_189;
 END;
 SYM AND2 num_and4[5];
   PIN Z0 OUT N_112;
   PIN A0 IN N_98_I_0;
   PIN A1 IN N_184;
 END;
 SYM AND2 num_and4[6];
   PIN Z0 OUT N_113;
   PIN A0 IN N_97_I_0_I;
   PIN A1 IN N_178;
 END;
 SYM AND2 num_and4_0[6];
   PIN Z0 OUT N_114;
   PIN A0 IN N_98_I_0;
   PIN A1 IN N_182;
 END;
 SYM AND2 num_and4[7];
   PIN Z0 OUT N_116;
   PIN A0 IN N_118;
   PIN A1 IN N_183;
 END;
 SYM AND2 un1_load_1;
   PIN Z0 OUT UN1_LOAD_1;
   PIN A0 IN LOAD;
   PIN A1 IN STATE_I[0];
 END;
 SYM AND2 un1_counta;
   PIN Z0 OUT UN1_COUNTA;
   PIN A0 IN COUNTA[0];
   PIN A1 IN COUNTA[1];
 END;
 SYM AND2 UQBN_B15;
   PIN Z0 OUT UQNN_N8;
   PIN A0 IN COUNT0_I[0];
   PIN A1 IN COUNT0_I[1];
 END;
 SYM AND2 _8_97;
   PIN Z0 OUT N_128_I;
   PIN A0 IN UQNN_N8;
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 _8;
   PIN Z0 OUT N_17_I_0;
   PIN A0 IN N_128_I;
   PIN A1 IN COUNT0_I[2];
 END;
 SYM AND2 _5;
   PIN Z0 OUT N_14;
   PIN A0 IN COUNT0[1];
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 _4;
   PIN Z0 OUT N_13_I_0;
   PIN A0 IN COUNT0_I[0];
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 un9_sel;
   PIN Z0 OUT UN9_SEL;
   PIN A0 IN COUNTA[1];
   PIN A1 IN COUNTA_I[0];
 END;
 SYM AND2 un3_sel;
   PIN Z0 OUT UN3_SEL;
   PIN A0 IN COUNTA[0];
   PIN A1 IN COUNTA_I[1];
 END;
 SYM AND2 un1_sel;
   PIN Z0 OUT UN1_SEL;
   PIN A0 IN COUNTA_I[0];
   PIN A1 IN COUNTA_I[1];
 END;
 SYM AND2 UQBN_B1;
   PIN Z0 OUT N_38;
   PIN A0 IN LOAD;
   PIN A1 IN UQNN_N13;
 END;
 SYM AND2 _15;
   PIN Z0 OUT N_24;
   PIN A0 IN N_19_I;
   PIN A1 IN COUNT1[2];
 END;
 SYM AND2 UQBN_B16;
   PIN Z0 OUT UQNN_N9;
   PIN A0 IN COUNT1_I[0];
   PIN A1 IN COUNT1_I[1];
 END;
 SYM XOR2 count1_n0;
   PIN Z0 OUT COUNT1_N0;
   PIN A0 IN N_19_I;
   PIN A1 IN _11_Z0;
 END;
 SYM XOR2 count1_n1;
   PIN Z0 OUT COUNT1_N1;
   PIN A0 IN N_21_I_0;
   PIN A1 IN _13_Z0;
 END;
 SYM XOR2 count1_n2;
   PIN Z0 OUT COUNT1_N2;
   PIN A0 IN N_23_I_0;
   PIN A1 IN N_24;
 END;
 SYM XOR2 count1_n3;
   PIN Z0 OUT COUNT1_N3;
   PIN A0 IN N_25_I_0;
   PIN A1 IN _17_Z0;
 END;
 SYM XOR2 state_0[0];
   PIN Z0 OUT N_5;
   PIN A0 IN UQNN_N7;
   PIN A1 IN STATE[0];
 END;
 SYM XOR2 next_state_1_2;
   PIN Z0 OUT NEXT_STATE[1];
   PIN A0 IN STATE_C[1];
   PIN A1 IN STATE_I[0];
 END;
 SYM XOR2 count0_n3;
   PIN Z0 OUT COUNT0_N3;
   PIN A0 IN N_17_I_0;
   PIN A1 IN _9_Z0;
 END;
 SYM XOR2 count0_n2;
   PIN Z0 OUT COUNT0_N2;
   PIN A0 IN _7_Z0;
   PIN A1 IN N_128_I;
 END;
 SYM XOR2 count0_n1;
   PIN Z0 OUT COUNT0_N1;
   PIN A0 IN N_13_I_0;
   PIN A1 IN N_14;
 END;
 SYM XOR2 count0_n0;
   PIN Z0 OUT COUNT0_N0;
   PIN A0 IN _3_Z0;
   PIN A1 IN UQNN_N11;
 END;
 SYM AND2 UQBN_B7;
   PIN Z0 OUT UQNN_N3;
   PIN A0 IN STATE_C[1];
   PIN A1 IN STATE_I[0];
 END;
 SYM AND2 UQBN_B3;
   PIN Z0 OUT UQNN_N4;
   PIN A0 IN STATE[0];
   PIN A1 IN STATE_C_I[1];
 END;
 SYM AND2 UQBN_B10;
   PIN Z0 OUT UQNN_N5;
   PIN A0 IN STATE_C_I[1];
   PIN A1 IN STATE_I[0];
 END;
 SYM AND2 un1_load_3;
   PIN Z0 OUT UN1_LOAD_3;
   PIN A0 IN LOAD;
   PIN A1 IN STATE[0];
 END;
 SYM AND2 UQBN_B20;
   PIN Z0 OUT UQNN_N11;
   PIN A0 IN LOAD_I;
   PIN A1 IN UQNN_N17;
 END;
 SYM AND2 UQBN_B21;
   PIN Z0 OUT N_19_I;
   PIN A0 IN LOAD_I;
   PIN A1 IN UQNN_N16;
 END;
 SYM AND2 UQBN_B13;
   PIN Z0 OUT UQNN_N7;
   PIN A0 IN UQNN_N6;
   PIN A1 IN UQNN_N10;
 END;
 SYM AND2 _12;
   PIN Z0 OUT N_21_I_0;
   PIN A0 IN N_19_I;
   PIN A1 IN COUNT1_I[0];
 END;
 SYM AND2 _14;
   PIN Z0 OUT N_23_I_0;
   PIN A0 IN N_19_I;
   PIN A1 IN UQNN_N9;
 END;
 SYM AND2 num_and4[4];
   PIN Z0 OUT N_110;
   PIN A0 IN N_96_I;
   PIN A1 IN N_97_I_0;
 END;
 SYM AND2 num_and4_0[4];
   PIN Z0 OUT N_111;
   PIN A0 IN N_98_I_0;
   PIN A1 IN N_119;