trafic.laf

来自「CPLD lattice1032 VHDL实现交通灯控制！」· LAF 代码 · 共 1,422 行 · 第 1/3 页

LAF 01.03.00 L;
SECTION HEADER ;
 DESIGN trafic 0.0 ;
 STAT edif2laf 1.0 6.12.2007 9.8.9 1 ;
END ;
SECTION DEVICE ;
 TECHNOLOGY pLSI;
 PART ispLSI1032E-70LJ84;
END ;
SECTION LOGICAL ;
  XPIN SEGOUT(0) OUT segout[0]_XO0 ;
  XPIN SEGOUT(1) OUT segout[1]_XO0 ;
  XPIN SEGOUT(2) OUT segout[2]_XO0 ;
  XPIN SEGOUT(3) OUT segout[3]_XO0 ;
  XPIN SEGOUT(4) OUT segout[4]_XO0 ;
  XPIN SEGOUT(5) OUT segout[5]_XO0 ;
  XPIN SEGOUT(6) OUT segout[6]_XO0 ;
  XPIN SEGOUT(7) OUT segout[7]_XO0 ;
  XPIN SELOUT(0) OUT selout[0]_XO0 ;
  XPIN SELOUT(1) OUT selout[1]_XO0 ;
  XPIN SELOUT(2) OUT selout[2]_XO0 ;
  XPIN SELOUT(3) OUT selout[3]_XO0 ;
  XPIN R1 OUT R1_XO0 ;
  XPIN R2 OUT R2_XO0 ;
  XPIN Y1 OUT Y1_XO0 ;
  XPIN Y2 OUT Y2_XO0 ;
  XPIN G1 OUT G1_XO0 ;
  XPIN G2 OUT G2_XO0 ;
  XPIN clk IN CLK ;
  XPIN clk1 IN CLK1 ;
  NET COUNTA[1]  SRC counta[1].Q0  DST un9_sel.A0 un1_counta.A1 counta_i[1].A0 I_93.A0 ;
  NET COUNTA[0]  SRC counta[0].Q0  DST un3_sel.A0 un1_counta.A0 counta_i[0].A0 I_91.A0 I_92.A0 temp[3]_$1I38.A0 temp[3]_$1I31.A1 temp[2]_$1I38.A0 temp[2]_$1I31.A1 temp[1]_$1I38.A0 temp[1]_$1I31.A1 temp[0]_$1I38.A0 temp[0]_$1I31.A1 ;
  NET COUNT0[1]  SRC count0[1].Q0  DST _5.A0 count0_i[1].A0 temp[1]_$1I25.A0 ;
  NET COUNT0[2]  SRC count0[2].Q0  DST count0_i[2].A0 temp[2]_$1I25.A0 _7_$1I31.A0 ;
  NET COUNT0[3]  SRC count0[3].Q0  DST count0_i[3].A0 temp[3]_$1I25.A0 _9_$1I31.A0 ;
  NET CARRY  SRC carry.Q0  DST carry_i.A0 count0[0].CLK count0[1].CLK count0[2].CLK count0[3].CLK count1[0].CLK count1[1].CLK count1[2].CLK count1[3].CLK ;
  NET COUNT1[1]  SRC count1[1].Q0  DST count1_i[1].A0 temp[1]_$1I31.A0 _13_$1I31.A0 count1_e1_$1I25.A0 ;
  NET COUNT1[2]  SRC count1[2].Q0  DST _15.A1 count1_i[2].A0 temp[2]_$1I31.A0 count1_e2_$1I25.A0 ;
  NET COUNT1[3]  SRC count1[3].Q0  DST count1_i[3].A0 temp[3]_$1I31.A0 count1_e3_$1I25.A0 _17_$1I31.A0 ;
  NET LOAD  SRC load.Q0  DST un1_load_3.A0 UQBN_B1.A0 un1_load_1.A0 load_i.A0 ;
  NET STATE[0]  SRC state[0].Q0  DST UQBN_B2.A0 un1_load_3.A1 UQBN_B3.A0 state_0[0].A1 state_i[0].A0 ;
  NET UN1_COUNTA  SRC un1_counta.Z0  DST un1_counta_i.A0 ;
  NET UQNN_N1  SRC UQBN_B4.Z0  DST carry.D0 ;
  NET COUNT[1]  SRC count[1].Q0  DST count_n1.A1 UQBN_B5.A1 ;
  NET COUNT[2]  SRC count[2].Q0  DST count_n2.A0 UQBN_B4.A0 ;
  NET UQNN_N2  SRC UQBN_B2.Z0  DST UQBN_B6.A0 ;
  NET UQNN_N3  SRC UQBN_B7.Z0  DST UQBN_B8.A0 ;
  NET UQNN_N4  SRC UQBN_B3.Z0  DST UQBN_B9.A0 ;
  NET UQNN_N5  SRC UQBN_B10.Z0  DST UQBN_B11.A0 ;
  NET UN1_SEL  SRC un1_sel.Z0  DST un1_sel_i.A0 ;
  NET UN3_SEL  SRC un3_sel.Z0  DST un3_sel_i.A0 ;
  NET UN9_SEL  SRC un9_sel.Z0  DST un9_sel_i.A0 ;
  NET UQNN_N6  SRC UQBN_B12.Z0  DST en.D0 UQBN_B13.A0 UQBN_B14.A0 ;
  NET EN  SRC en.Q0  DST count1_e3_$1I38.A0 count1_e3_$1I31.A1 count1_e0_$1I38.A0 count1_e0_$1I31.A1 count1_e1_$1I38.A0 count1_e1_$1I31.A1 count1_e2_$1I38.A0 count1_e2_$1I31.A1 ;
  NET UN6_COUNTA[2]  SRC I_91.Z0  DST counta[0].D0 ;
  NET UN6_COUNTA[1]  SRC I_93.Z0  DST counta[1].D0 ;
  NET UQNN_N7  SRC UQBN_B13.Z0  DST state_0[0].A0 load.D0 state_0[1]_$1I38.A0 state_0[1]_$1I31.A1 ;
  NET N_5  SRC state_0[0].Z0  DST state[0].D0 ;
  NET COUNT_N1  SRC count_n1.Z0  DST count[1].D0 ;
  NET COUNT_N2  SRC count_n2.Z0  DST count[2].D0 ;
  NET COUNT0_N0  SRC count0_n0.Z0  DST count0[0].D0 ;
  NET COUNT0_N1  SRC count0_n1.Z0  DST count0[1].D0 ;
  NET COUNT0_N2  SRC count0_n2.Z0  DST count0[2].D0 ;
  NET COUNT0_N3  SRC count0_n3.Z0  DST count0[3].D0 ;
  NET N_80  SRC num_38_i_and2.Z0  DST N_80_i.A0 ;
  NET N_96  SRC num_85.Z0  DST N_96_i.A0 ;
  NET N_102  SRC num_and4[1].Z0  DST N_102_i.A0 ;
  NET N_103  SRC num_and4_0[1].Z0  DST N_103_i.A0 ;
  NET N_104  SRC num_and4_1[1].Z0  DST N_104_i.A0 ;
  NET N_105  SRC num_i_and4[2].Z0  DST N_105_i.A0 ;
  NET N_106  SRC num_i_and4_0[2].Z0  DST N_106_i.A0 ;
  NET N_107  SRC num_i_and4_1[2].Z0  DST N_107_i.A0 ;
  NET N_108  SRC num_and4[3].Z0  DST N_108_i.A0 ;
  NET N_109  SRC num_and4_0[3].Z0  DST N_109_i.A0 ;
  NET N_110  SRC num_and4[4].Z0  DST N_110_i.A0 ;
  NET N_111  SRC num_and4_0[4].Z0  DST N_111_i.A0 ;
  NET N_112  SRC num_and4[5].Z0  DST N_112_i.A0 ;
  NET N_113  SRC num_and4[6].Z0  DST N_113_i.A0 ;
  NET N_114  SRC num_and4_0[6].Z0  DST N_114_i.A0 ;
  NET N_115  SRC num_and4_1[6].Z0  DST N_115_i.A0 ;
  NET N_116  SRC num_and4[7].Z0  DST N_116_i.A0 ;
  NET N_118  SRC num_82.Z0  DST num_and4[1].A0 num_and4_1[6].A1 num_and4[7].A0 ;
  NET N_119  SRC num_83.Z0  DST num_84.A0 num_and4_0[4].A1 ;
  NET N_120  SRC num_84.Z0  DST num_and4_1[1].A0 N_120_i.A0 ;
  NET N_123  SRC I_92.Z0  DST I_93.A1 ;
  NET COUNT0[0]  SRC count0[0].Q0  DST count0_i[0].A0 temp[0]_$1I25.A0 _3_$1I31.A0 ;
  NET COUNT1[0]  SRC count1[0].Q0  DST count1_i[0].A0 temp[0]_$1I31.A0 _11_$1I31.A0 count1_e0_$1I25.A0 ;
  NET COUNT[0]  SRC count[0].Q0  DST count_n1.A0 UQBN_B5.A0 count_i[0].A0 ;
  NET COUNT_C1  SRC UQBN_B5.Z0  DST count_n2.A1 UQBN_B4.A1 ;
  NET UN1_LOAD_1  SRC un1_load_1.Z0  DST _7_$1I25.A0 ;
  NET N_14  SRC _5.Z0  DST count0_n1.A1 ;
  NET UQNN_N8  SRC UQBN_B15.Z0  DST _8_97.A0 UQBN_B12.A0 ;
  NET N_24  SRC _15.Z0  DST count1_n2.A1 ;
  NET NEXT_STATE[1]  SRC next_state_1_2.Z0  DST state_0[1]_$1I31.A0 ;
  NET COUNT1_N3  SRC count1_n3.Z0  DST count1_e3_$1I31.A0 ;
  NET COUNT1_N2  SRC count1_n2.Z0  DST count1_e2_$1I31.A0 ;
  NET UQNN_N9  SRC UQBN_B16.Z0  DST _14.A1 _16_120.A1 UQBN_B17.A0 ;
  NET COUNT1_N1  SRC count1_n1.Z0  DST count1_e1_$1I31.A0 ;
  NET COUNT1_N0  SRC count1_n0.Z0  DST count1_e0_$1I31.A0 ;
  NET N_38  SRC UQBN_B1.Z0  DST UQBN_B18.A0 ;
  NET UQNN_N10  SRC UQBN_B17.Z0  DST UQBN_B13.A1 UQBN_B19.A0 ;
  NET UN1_LOAD_3  SRC un1_load_3.Z0  DST _13_$1I25.A0 ;
  NET CLK  EXT  DST clk_$1I45.XI0 ;
  NET CLK1  EXT  DST clk1_$1I45.XI0 ;
  NET STATE_C[1]  SRC state[1].Q0  DST UQBN_B2.A1 UQBN_B7.A0 next_state_1_2.A0 state_c_i[1].A0 R1_$1I42.A0 state_0[1]_$1I25.A0 ;
  NET NUM_C[1]  SRC num_31.Z0  DST segout[1]_$1I42.A0 ;
  NET NUM_C[2]  SRC num_32.Z0  DST segout[2]_$1I42.A0 ;
  NET VCC  DST I_91.A1 I_92.A1 segout[0]_$1I42.A0 ;
  NET N_141  SRC num[1].Z0  DST N_141_i.A0 ;
  NET N_143  SRC num[7].Z0  DST N_143_i.A0 ;
  NET N_145  SRC num_36.Z0  DST N_145_i.A0 ;
  NET N_148  SRC num_34.Z0  DST N_148_i.A0 ;
  NET N_150  SRC num_35.Z0  DST N_150_i.A0 ;
  NET N_155  SRC num[3].Z0  DST N_155_i.A0 ;
  NET UQNN_N11  SRC UQBN_B20.Z0  DST count0_n0.A1 _4.A1 _5.A1 _8_97.A1 _9_$1I38.A0 _9_$1I31.A1 _7_$1I38.A0 _7_$1I31.A1 _3_$1I38.A0 _3_$1I31.A1 ;
  NET N_13_I_0  SRC _4.Z0  DST count0_n1.A0 ;
  NET N_128_I  SRC _8_97.Z0  DST count0_n2.A1 _8.A0 ;
  NET N_17_I_0  SRC _8.Z0  DST count0_n3.A0 ;
  NET N_25_I_0  SRC _16.Z0  DST count1_n3.A0 ;
  NET N_23_I_0  SRC _14.Z0  DST count1_n2.A0 ;
  NET N_21_I_0  SRC _12.Z0  DST count1_n1.A0 ;
  NET N_19_I  SRC UQBN_B21.Z0  DST _14.A0 _12.A0 count1_n0.A0 _15.A0 _16.A0 _11_$1I38.A0 _11_$1I31.A1 _13_$1I38.A0 _13_$1I31.A1 _17_$1I38.A0 _17_$1I31.A1 ;
  NET N_98_I_0  SRC num_87.Z0  DST num_and4_0[4].A0 num_and4_0[6].A0 num_and4[5].A0 N_98_i_0_i.A0 ;
  NET N_97_I_0  SRC num_86.Z0  DST num_i_and4_1[2].A0 num_and4_0[1].A0 num_and4_1[6].A0 num_and4[4].A1 N_97_i_0_i.A0 ;
  NET N_175  SRC UQBN_B22.Z0  DST UQBN_B17.A1 ;
  NET N_176  SRC UQBN_B23.Z0  DST UQBN_B12.A1 ;
  NET N_177  SRC _16_120.Z0  DST _16.A1 ;
  NET N_178  SRC num_and4_6_121.Z0  DST num_and4[6].A1 ;
  NET N_179  SRC num_38_i_and2_122.Z0  DST num_38_i_and2.A0 ;
  NET N_180  SRC num_38_i_and2_123.Z0  DST num_38_i_and2.A1 ;
  NET N_181  SRC num_and4_0_3_124.Z0  DST num_and4_0[3].A1 ;
  NET N_182  SRC num_and4_0_6_125.Z0  DST num_and4_0[6].A1 ;
  NET N_183  SRC num_and4_7_126.Z0  DST num_and4[7].A1 ;
  NET N_184  SRC num_and4_5_127.Z0  DST num_and4[5].A1 ;
  NET N_185  SRC num_36_128.Z0  DST num_36.A0 ;
  NET N_186  SRC num_36_129.Z0  DST num_36.A1 ;
  NET N_187  SRC num_7_130.Z0  DST num[7].A1 ;
  NET N_188  SRC num_1_131.Z0  DST num[1].A1 ;
  NET N_189  SRC num_34_132.Z0  DST num_34.A1 ;
  NET N_190  SRC num_35_133.Z0  DST num_35.A1 ;
  NET N_191  SRC num_32_134.Z0  DST num_32.A0 ;
  NET N_192  SRC num_32_135.Z0  DST num_32.A1 ;
  NET N_193  SRC num_3_136.Z0  DST num[3].A1 ;
  NET N_108_I  SRC N_108_i.ZN0  DST num_3_136.A0 ;
  NET N_109_I  SRC N_109_i.ZN0  DST num_3_136.A1 ;
  NET N_80_I  SRC N_80_i.ZN0  DST num_31.A0 num_35.A0 num_32_135.A0 num_36_128.A1 ;
  NET N_107_I  SRC N_107_i.ZN0  DST num[3].A0 num_32_135.A1 ;
  NET N_106_I  SRC N_106_i.ZN0  DST num_32_134.A0 ;
  NET N_105_I  SRC N_105_i.ZN0  DST num_32_134.A1 ;
  NET N_120_I  SRC N_120_i.ZN0  DST num_35_133.A0 ;
  NET N_112_I  SRC N_112_i.ZN0  DST num_35_133.A1 ;
  NET N_111_I  SRC N_111_i.ZN0  DST num_34_132.A0 ;
  NET N_102_I  SRC N_102_i.ZN0  DST num_34_132.A1 num_1_131.A1 ;
  NET N_103_I  SRC N_103_i.ZN0  DST num_1_131.A0 ;
  NET N_116_I  SRC N_116_i.ZN0  DST num_7_130.A0 ;
  NET N_114_I  SRC N_114_i.ZN0  DST num_7_130.A1 num_36_129.A1 ;
  NET N_115_I  SRC N_115_i.ZN0  DST num_36_129.A0 ;
  NET N_113_I  SRC N_113_i.ZN0  DST num_36_128.A0 ;
  NET TEMP_I[3]  SRC temp_i[3].ZN0  DST num_and4[3].A1 num_86.A1 num_and4_5_127.A0 ;
  NET TEMP_I[0]  SRC temp_i[0].ZN0  DST num_i_and4[2].A1 num_83.A1 num_85.A1 num_and4_6_121.A0 num_and4_5_127.A1 ;
  NET TEMP_I[1]  SRC temp_i[1].ZN0  DST num_and4_1[1].A1 num_86.A0 num_and4_0[3].A0 num_and4_7_126.A0 ;
  NET TEMP_I[2]  SRC temp_i[2].ZN0  DST num_i_and4_0[2].A1 num_and4_0[1].A1 num_87.A1 num_and4_0_3_124.A1 ;
  NET COUNT1_I[2]  SRC count1_i[2].ZN0  DST _16_120.A0 UQBN_B22.A1 ;
  NET COUNT0_I[3]  SRC count0_i[3].ZN0  DST UQBN_B23.A0 ;
  NET COUNT0_I[2]  SRC count0_i[2].ZN0  DST _8.A1 UQBN_B23.A1 ;
  NET COUNT1_I[3]  SRC count1_i[3].ZN0  DST UQBN_B22.A0 ;
  NET N_104_I  SRC N_104_i.ZN0  DST num[1].A0 ;
  NET N_110_I  SRC N_110_i.ZN0  DST num_34.A0 num[7].A0 ;
  NET N_97_I_0_I  SRC N_97_i_0_i.ZN0  DST num_and4[6].A0 ;
  NET UN1_COUNTA_I  SRC un1_counta_i.ZN0  DST selout[3]_$1I42.A0 ;
  NET UN9_SEL_I  SRC un9_sel_i.ZN0  DST selout[2]_$1I42.A0 ;
  NET UN3_SEL_I  SRC un3_sel_i.ZN0  DST selout[1]_$1I42.A0 ;
  NET UN1_SEL_I  SRC un1_sel_i.ZN0  DST selout[0]_$1I42.A0 ;
  NET N_143_I  SRC N_143_i.ZN0  DST segout[7]_$1I42.A0 ;
  NET N_145_I  SRC N_145_i.ZN0  DST segout[6]_$1I42.A0 ;
  NET N_150_I  SRC N_150_i.ZN0  DST segout[5]_$1I42.A0 ;
  NET N_148_I  SRC N_148_i.ZN0  DST segout[4]_$1I42.A0 ;
  NET N_155_I  SRC N_155_i.ZN0  DST segout[3]_$1I42.A0 ;
  NET UQNN_N12  SRC UQBN_B9.ZN0  DST G2_$1I42.A0 ;
  NET UQNN_N13  SRC UQBN_B6.ZN0  DST UQBN_B1.A1 G1_$1I42.A0 ;
  NET UQNN_N14  SRC UQBN_B11.ZN0  DST Y2_$1I42.A0 ;
  NET UQNN_N15  SRC UQBN_B8.ZN0  DST Y1_$1I42.A0 ;
  NET STATE_C_I[1]  SRC state_c_i[1].ZN0  DST UQBN_B10.A0 UQBN_B3.A1 R2_$1I42.A0 ;
  NET STATE_I[0]  SRC state_i[0].ZN0  DST UQBN_B10.A1 UQBN_B7.A1 next_state_1_2.A1 un1_load_1.A1 ;
  NET COUNTA_I[0]  SRC counta_i[0].ZN0  DST un1_sel.A0 un9_sel.A1 ;
  NET COUNTA_I[1]  SRC counta_i[1].ZN0  DST un1_sel.A1 un3_sel.A1 ;
  NET LOAD_I  SRC load_i.ZN0  DST UQBN_B21.A0 UQBN_B20.A0 _9_$1I25.A0 _3_$1I25.A0 _17_$1I25.A0 ;
  NET COUNT0_I[0]  SRC count0_i[0].ZN0  DST _4.A0 UQBN_B15.A0 ;
  NET COUNT0_I[1]  SRC count0_i[1].ZN0  DST UQBN_B15.A1 ;
  NET COUNT1_I[0]  SRC count1_i[0].ZN0  DST _12.A1 UQBN_B16.A0 ;
  NET COUNT1_I[1]  SRC count1_i[1].ZN0  DST UQBN_B16.A1 ;
  NET N_38_I  SRC UQBN_B18.ZN0  DST _11_$1I25.A0 ;
  NET UQNN_N16  SRC UQBN_B19.ZN0  DST UQBN_B21.A1 ;
  NET UQNN_N17  SRC UQBN_B14.ZN0  DST UQBN_B20.A1 ;
  NET N_141_I  SRC N_141_i.ZN0  DST num_31.A1 ;
  NET N_96_I  SRC N_96_i.ZN0  DST num_and4[4].A0 ;
  NET N_98_I_0_I  SRC N_98_i_0_i.ZN0  DST num_i_and4[2].A0 ;
  NET CARRY_I  SRC carry_i.ZN0  DST en.G state[0].CLK state[1].CLK load.CLK ;
  NET COUNT_I[0]  SRC count_i[0].ZN0  DST count[0].D0 ;
  NET GND ;
  NET clk_Z0  SRC clk_$1I45.Z0  DST carry.CLK count[0].CLK count[1].CLK count[2].CLK ;
  NET clk1_Z0  SRC clk1_$1I45.Z0  DST counta[0].CLK counta[1].CLK ;
  NET R1_XO0 EXT  SRC R1_$1I42.XO0 ;
  NET R2_XO0 EXT  SRC R2_$1I42.XO0 ;
  NET Y1_XO0 EXT  SRC Y1_$1I42.XO0 ;
  NET Y2_XO0 EXT  SRC Y2_$1I42.XO0 ;
  NET G1_XO0 EXT  SRC G1_$1I42.XO0 ;
  NET G2_XO0 EXT  SRC G2_$1I42.XO0 ;
  NET segout[0]_XO0 EXT  SRC segout[0]_$1I42.XO0 ;
  NET segout[1]_XO0 EXT  SRC segout[1]_$1I42.XO0 ;
  NET segout[2]_XO0 EXT  SRC segout[2]_$1I42.XO0 ;
  NET segout[3]_XO0 EXT  SRC segout[3]_$1I42.XO0 ;
  NET segout[4]_XO0 EXT  SRC segout[4]_$1I42.XO0 ;
  NET segout[5]_XO0 EXT  SRC segout[5]_$1I42.XO0 ;
  NET segout[6]_XO0 EXT  SRC segout[6]_$1I42.XO0 ;
  NET segout[7]_XO0 EXT  SRC segout[7]_$1I42.XO0 ;
  NET selout[0]_XO0 EXT  SRC selout[0]_$1I42.XO0 ;
  NET selout[1]_XO0 EXT  SRC selout[1]_$1I42.XO0 ;
  NET selout[2]_XO0 EXT  SRC selout[2]_$1I42.XO0 ;
  NET selout[3]_XO0 EXT  SRC selout[3]_$1I42.XO0 ;
  NET temp[3]_Z0  SRC temp[3]_$1I35.Z0  DST num_i_and4_0[2].A0 num_83.A0 num_38_i_and2_123.A0 num_and4_7_126.A1 num_and4_0_6_125.A0 temp_i[3].A0 ;
  NET temp[3]_$1N8  SRC temp[3]_$1I31.Z0  DST temp[3]_$1I35.A1 ;
  NET temp[3]_$1N6  SRC temp[3]_$1I25.Z0  DST temp[3]_$1I35.A0 ;
  NET temp[3]_$1N22  SRC temp[3]_$1I38.ZN0  DST temp[3]_$1I25.A1 ;
  NET temp[2]_Z0  SRC temp[2]_$1I35.Z0  DST num_i_and4_1[2].A1 num_84.A1 num_82.A1 num_85.A0 num_38_i_and2_123.A1 num_and4_6_121.A1 temp_i[2].A0 ;
  NET temp[2]_$1N8  SRC temp[2]_$1I31.Z0  DST temp[2]_$1I35.A1 ;
  NET temp[2]_$1N6  SRC temp[2]_$1I25.Z0  DST temp[2]_$1I35.A0 ;
  NET temp[2]_$1N22  SRC temp[2]_$1I38.ZN0  DST temp[2]_$1I25.A1 ;
  NET temp[1]_Z0  SRC temp[1]_$1I35.Z0  DST num_and4[1].A1 num_87.A0 num_38_i_and2_122.A0 temp_i[1].A0 ;
  NET temp[1]_$1N8  SRC temp[1]_$1I31.Z0  DST temp[1]_$1I35.A1 ;
  NET temp[1]_$1N6  SRC temp[1]_$1I25.Z0  DST temp[1]_$1I35.A0 ;
  NET temp[1]_$1N22  SRC temp[1]_$1I38.ZN0  DST temp[1]_$1I25.A1 ;
  NET temp[0]_Z0  SRC temp[0]_$1I35.Z0  DST num_and4[3].A0 num_82.A0 num_and4_0_3_124.A0 num_38_i_and2_122.A1 num_and4_0_6_125.A1 temp_i[0].A0 ;
  NET temp[0]_$1N8  SRC temp[0]_$1I31.Z0  DST temp[0]_$1I35.A1 ;
  NET temp[0]_$1N6  SRC temp[0]_$1I25.Z0  DST temp[0]_$1I35.A0 ;
  NET temp[0]_$1N22  SRC temp[0]_$1I38.ZN0  DST temp[0]_$1I25.A1 ;
  NET _9_Z0  SRC _9_$1I35.Z0  DST count0_n3.A1 ;
  NET _9_$1N8  SRC _9_$1I31.Z0  DST _9_$1I35.A1 ;
  NET _9_$1N6  SRC _9_$1I25.Z0  DST _9_$1I35.A0 ;
  NET _9_$1N22  SRC _9_$1I38.ZN0  DST _9_$1I25.A1 ;
  NET _7_Z0  SRC _7_$1I35.Z0  DST count0_n2.A0 ;
  NET _7_$1N8  SRC _7_$1I31.Z0  DST _7_$1I35.A1 ;
  NET _7_$1N6  SRC _7_$1I25.Z0  DST _7_$1I35.A0 ;
  NET _7_$1N22  SRC _7_$1I38.ZN0  DST _7_$1I25.A1 ;
  NET _3_Z0  SRC _3_$1I35.Z0  DST count0_n0.A0 ;
  NET _3_$1N8  SRC _3_$1I31.Z0  DST _3_$1I35.A1 ;
  NET _3_$1N6  SRC _3_$1I25.Z0  DST _3_$1I35.A0 ;
  NET _3_$1N22  SRC _3_$1I38.ZN0  DST _3_$1I25.A1 ;
  NET count1_e3_Z0  SRC count1_e3_$1I35.Z0  DST count1[3].D0 ;
  NET count1_e3_$1N8  SRC count1_e3_$1I31.Z0  DST count1_e3_$1I35.A1 ;
  NET count1_e3_$1N6  SRC count1_e3_$1I25.Z0  DST count1_e3_$1I35.A0 ;
  NET count1_e3_$1N22  SRC count1_e3_$1I38.ZN0  DST count1_e3_$1I25.A1 ;
  NET state_0[1]_Z0  SRC state_0[1]_$1I35.Z0  DST state[1].D0 ;
  NET state_0[1]_$1N8  SRC state_0[1]_$1I31.Z0  DST state_0[1]_$1I35.A1 ;
  NET state_0[1]_$1N6  SRC state_0[1]_$1I25.Z0  DST state_0[1]_$1I35.A0 ;
  NET state_0[1]_$1N22  SRC state_0[1]_$1I38.ZN0  DST state_0[1]_$1I25.A1 ;
  NET _11_Z0  SRC _11_$1I35.Z0  DST count1_n0.A1 ;
  NET _11_$1N8  SRC _11_$1I31.Z0  DST _11_$1I35.A1 ;
  NET _11_$1N6  SRC _11_$1I25.Z0  DST _11_$1I35.A0 ;
  NET _11_$1N22  SRC _11_$1I38.ZN0  DST _11_$1I25.A1 ;
  NET count1_e0_Z0  SRC count1_e0_$1I35.Z0  DST count1[0].D0 ;
  NET count1_e0_$1N8  SRC count1_e0_$1I31.Z0  DST count1_e0_$1I35.A1 ;
  NET count1_e0_$1N6  SRC count1_e0_$1I25.Z0  DST count1_e0_$1I35.A0 ;
  NET count1_e0_$1N22  SRC count1_e0_$1I38.ZN0  DST count1_e0_$1I25.A1 ;
  NET _13_Z0  SRC _13_$1I35.Z0  DST count1_n1.A1 ;
  NET _13_$1N8  SRC _13_$1I31.Z0  DST _13_$1I35.A1 ;
  NET _13_$1N6  SRC _13_$1I25.Z0  DST _13_$1I35.A0 ;
  NET _13_$1N22  SRC _13_$1I38.ZN0  DST _13_$1I25.A1 ;
  NET count1_e1_Z0  SRC count1_e1_$1I35.Z0  DST count1[1].D0 ;
  NET count1_e1_$1N8  SRC count1_e1_$1I31.Z0  DST count1_e1_$1I35.A1 ;
  NET count1_e1_$1N6  SRC count1_e1_$1I25.Z0  DST count1_e1_$1I35.A0 ;
  NET count1_e1_$1N22  SRC count1_e1_$1I38.ZN0  DST count1_e1_$1I25.A1 ;
  NET count1_e2_Z0  SRC count1_e2_$1I35.Z0  DST count1[2].D0 ;
  NET count1_e2_$1N8  SRC count1_e2_$1I31.Z0  DST count1_e2_$1I35.A1 ;
  NET count1_e2_$1N6  SRC count1_e2_$1I25.Z0  DST count1_e2_$1I35.A0 ;
  NET count1_e2_$1N22  SRC count1_e2_$1I38.ZN0  DST count1_e2_$1I25.A1 ;
  NET _17_Z0  SRC _17_$1I35.Z0  DST count1_n3.A1 ;
  NET _17_$1N8  SRC _17_$1I31.Z0  DST _17_$1I35.A1 ;
  NET _17_$1N6  SRC _17_$1I25.Z0  DST _17_$1I35.A0 ;
  NET _17_$1N22  SRC _17_$1I38.ZN0  DST _17_$1I25.A1 ;
 SYM FD11 counta[1];
   PIN Q0 OUT COUNTA[1];
   PIN CLK IN clk1_Z0;
   PIN D0 IN UN6_COUNTA[1];
 END;
 SYM FD11 state[0];
   PIN Q0 OUT STATE[0];
   PIN CLK IN CARRY_I;
   PIN D0 IN N_5;
 END;
 SYM FD11 state[1];
   PIN Q0 OUT STATE_C[1];
   PIN CLK IN CARRY_I;
   PIN D0 IN state_0[1]_Z0;
 END;
 SYM FD11 count1[1];
   PIN Q0 OUT COUNT1[1];
   PIN CLK IN CARRY;
   PIN D0 IN count1_e1_Z0;
 END;
 SYM FD11 count1[2];
   PIN Q0 OUT COUNT1[2];
   PIN CLK IN CARRY;
   PIN D0 IN count1_e2_Z0;
 END;
 SYM FD11 count1[3];
   PIN Q0 OUT COUNT1[3];
   PIN CLK IN CARRY;
   PIN D0 IN count1_e3_Z0;
 END;
 SYM FD11 counta[0];
   PIN Q0 OUT COUNTA[0];
   PIN CLK IN clk1_Z0;
   PIN D0 IN UN6_COUNTA[2];
 END;
 SYM FD11 count0[3];
   PIN Q0 OUT COUNT0[3];
   PIN CLK IN CARRY;
   PIN D0 IN COUNT0_N3;
 END;
 SYM FD11 count1[0];
   PIN Q0 OUT COUNT1[0];
   PIN CLK IN CARRY;
   PIN D0 IN count1_e0_Z0;
 END;
 SYM FD11 count0[1];
   PIN Q0 OUT COUNT0[1];
   PIN CLK IN CARRY;
   PIN D0 IN COUNT0_N1;
 END;
 SYM FD11 count0[2];
   PIN Q0 OUT COUNT0[2];
   PIN CLK IN CARRY;
   PIN D0 IN COUNT0_N2;
 END;
 SYM FD11 count[0];
   PIN Q0 OUT COUNT[0];
   PIN CLK IN clk_Z0;
   PIN D0 IN COUNT_I[0];
 END;
 SYM FD11 count[1];
   PIN Q0 OUT COUNT[1];
   PIN CLK IN clk_Z0;
   PIN D0 IN COUNT_N1;
 END;
 SYM FD11 count[2];
   PIN Q0 OUT COUNT[2];
   PIN CLK IN clk_Z0;
   PIN D0 IN COUNT_N2;
 END;
 SYM FD11 count0[0];
   PIN Q0 OUT COUNT0[0];
   PIN CLK IN CARRY;
   PIN D0 IN COUNT0_N0;
 END;
 SYM FD11 load;
   PIN Q0 OUT LOAD;
   PIN CLK IN CARRY_I;
   PIN D0 IN UQNN_N7;
 END;
 SYM FD11 carry;
   PIN Q0 OUT CARRY;
   PIN CLK IN clk_Z0;
   PIN D0 IN UQNN_N1;
 END;
 SYM XOR2 I_91;
   PIN Z0 OUT UN6_COUNTA[2];
   PIN A0 IN COUNTA[0];
   PIN A1 IN VCC;
 END;
 SYM AND2 I_92;
   PIN Z0 OUT N_123;
   PIN A0 IN COUNTA[0];
   PIN A1 IN VCC;
 END;
 SYM XOR2 I_93;
   PIN Z0 OUT UN6_COUNTA[1];
   PIN A0 IN COUNTA[1];
   PIN A1 IN N_123;
 END;
 SYM INV UQBN_B18;
   PIN ZN0 OUT N_38_I;
   PIN A0 IN N_38;
 END;
 SYM INV UQBN_B19;
   PIN ZN0 OUT UQNN_N16;
   PIN A0 IN UQNN_N10;
 END;
 SYM INV UQBN_B14;
   PIN ZN0 OUT UQNN_N17;
   PIN A0 IN UQNN_N6;
 END;
 SYM INV N_141_i;
   PIN ZN0 OUT N_141_I;
   PIN A0 IN N_141;
 END;
 SYM INV N_96_i;
   PIN ZN0 OUT N_96_I;
   PIN A0 IN N_96;
 END;
 SYM INV N_98_i_0_i;
   PIN ZN0 OUT N_98_I_0_I;
   PIN A0 IN N_98_I_0;
 END;
 SYM INV carry_i;
   PIN ZN0 OUT CARRY_I;
   PIN A0 IN CARRY;
 END;
 SYM INV count_i[0];
   PIN ZN0 OUT COUNT_I[0];
   PIN A0 IN COUNT[0];
 END;
 SYM INV N_148_i;
   PIN ZN0 OUT N_148_I;
   PIN A0 IN N_148;
 END;
 SYM INV N_155_i;
   PIN ZN0 OUT N_155_I;
   PIN A0 IN N_155;
 END;
 SYM INV UQBN_B9;
   PIN ZN0 OUT UQNN_N12;
   PIN A0 IN UQNN_N4;
 END;
 SYM INV UQBN_B6;
   PIN ZN0 OUT UQNN_N13;
   PIN A0 IN UQNN_N2;
 END;
 SYM INV UQBN_B11;
   PIN ZN0 OUT UQNN_N14;
   PIN A0 IN UQNN_N5;
 END;
 SYM INV UQBN_B8;
   PIN ZN0 OUT UQNN_N15;
   PIN A0 IN UQNN_N3;
 END;
 SYM INV state_c_i[1];
   PIN ZN0 OUT STATE_C_I[1];
   PIN A0 IN STATE_C[1];
 END;
 SYM INV state_i[0];
   PIN ZN0 OUT STATE_I[0];
   PIN A0 IN STATE[0];
 END;
 SYM INV counta_i[0];
   PIN ZN0 OUT COUNTA_I[0];
   PIN A0 IN COUNTA[0];
 END;
 SYM INV counta_i[1];
   PIN ZN0 OUT COUNTA_I[1];
   PIN A0 IN COUNTA[1];
 END;
 SYM INV load_i;
   PIN ZN0 OUT LOAD_I;
   PIN A0 IN LOAD;
 END;
 SYM INV count0_i[0];
   PIN ZN0 OUT COUNT0_I[0];
   PIN A0 IN COUNT0[0];
 END;
 SYM INV count0_i[1];
   PIN ZN0 OUT COUNT0_I[1];
   PIN A0 IN COUNT0[1];
 END;
 SYM INV count1_i[0];
   PIN ZN0 OUT COUNT1_I[0];
   PIN A0 IN COUNT1[0];
 END;
 SYM INV count1_i[1];
   PIN ZN0 OUT COUNT1_I[1];
   PIN A0 IN COUNT1[1];
 END;
 SYM INV temp_i[2];
   PIN ZN0 OUT TEMP_I[2];