trafic.vhd

来自「CPLD lattice1032 VHDL实现交通灯控制！」· VHDL 代码 · 共 181 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity trafic is
	port (	clk,clk1:in	std_logic;
		R1,R2,Y1,Y2,G1,G2:out std_logic;
		segout:out std_logic_vector(7 downto 0);
		selout:out std_logic_vector(3 downto 0));
--		A,B:	out std_logic_vector(3 downto 0));
end;

architecture arch of trafic is

type states is (s3,s2,s1,s0);
signal state:		states:=s0;
signal next_state:	states:=s0;

signal	count:std_logic_vector(2 downto 0);
signal counta:std_logic_vector(1 downto 0);
signal sel:std_logic_vector(3 downto 0);
signal temp:std_logic_vector(3 downto 0);
signal num:std_logic_vector(7 downto 0);
signal	count0:	std_logic_vector(3 downto 0):="0000";
signal	count1:	std_logic_vector(3 downto 0):="0000";
signal	data0:	std_logic_vector(3 downto 0):="0000";
signal	data1:	std_logic_vector(3 downto 0):="0000";
signal 	light:	std_logic_vector(5 downto 0);


signal	en,load,carry:	std_logic;

begin

process(clk1)
begin
	if(rising_edge(clk1))then
		if(counta="11")then 
			counta<="00";
		else
			counta<=counta+'1';
		end if;
	end if;
end process;

	p1:process(clk)
	begin
			if rising_edge (clk) then
				count <= count+'1';
			end if;

	end process p1;

	p11:process (clk)
	begin
			if rising_edge (clk) then
				if count="111" then
					carry<='1';
				else
					carry<='0';
				end if;
			end if;
	end process p11;

	p2:process(carry,load)
		begin
			if rising_edge (carry) then
				if load ='1' then
					count0<=data0;
				elsif count0="0000" then
					count0<="1001";	
					else
					count0<=count0-'1';
				end  if;
			end if;
		end process p2;

	p22:process(carry,count0)
	begin
		if carry='0' then
			if count0="0000" then
				en<='1';
				else
				en<='0';
			end if;
		end if;
	end process p22;

	p3:process(carry,en)
		begin
			if (rising_edge (carry) and en='1') then
				if load ='1' then
					count1<=data1;
				elsif count1="0000" then
					count1<="1001";
					else
					count1<=count1-'1';
				end  if;
			end if;
	end process p3;	

	p4:process(carry)
		begin
			if (falling_edge (carry) ) then
				if( count0 ="0000" and  count1 ="0000") then
					load<='1';
				state<=next_state;
				else
					load<='0';
				end  if;
			end if;
	end process p4;	

	p6:process(state)
		begin			
			case state is
				when s0 => light <="001100";
					next_state<=s1;
					data0<="0000";
					data1<="0011";

				when s1 => light <="010100";
					next_state<=s2;
					data0<="0100";
					data1<="0000";

				when s2 => light <="100001";
					next_state<=s3;
					data0<="0000";
					data1<="0010";

				when s3 => light <="100010";
					next_state<=s0;
					data0<="0100";
					data1<="0000";
			end case;
	end process p6;

SEL<="1110" when counta="00" else
		"1101" when counta="01" else
		"1011" when counta="10" else
		"0111" when counta="11";


temp<=	count0 when SEL="1110" else
	count1 when sel="1101" else
	count0 when sel="1011" else		
	count1 when SEL="0111";	

WITH temp select
	NUM  <="00000011" WHEN "0000",
			   "10011111" WHEN "0001",
			   "00100101" WHEN "0010",
			   "00001101" WHEN "0011",
			   "10011001" WHEN "0100",
			   "01001001" WHEN "0101",
			   "01000001" WHEN "0110",
			   "00011111" WHEN "0111",
			   "00000001" WHEN "1000",
			   "00001001" WHEN "1001",
			   "00010001" WHEN "1010",
			   "11000001" WHEN "1011",
			   "01100011" WHEN "1100",
			   "10000101" WHEN "1101",
			   "01100001" WHEN "1110",
			   "01110001" WHEN OTHERS;
--	A<=count0;
--	B<=count1;
	selout<=sel;
	segout<=num;
	R1<=not light(5);
	Y1<=not light(4);
	G1<=not light(3);
	R2<=not light(2);
	Y2<=not light(1);
	G2<=not light(0);
end arch;