ta.log

CPLD lattice1032 VHDL实现交通灯控制！

Timing Analyzer Software 
Copyright (c) 1999 by Lattice Semiconductor Corporation 
All Rights Reserved 

Reading design trafic .... 

43121 WARNING: Design has combinational cycles

Evaluating maximum operating frequency...
Evaluating setup and hold times...
43006 WARNING: No chip input pins drive data input and clock input of any register

Calculating  Tpd Path delays ...

Calculating  Tco Path delays ...

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Timing analyzer completed successfully