trafic.ldb

CPLD lattice1032 VHDL实现交通灯控制！

DESIGN TRAFIC
{
    PORT clk input 
    {
        ATTR LOCK string 2
20

        {

        }

    }
    PORT G2 output 
    {
        ATTR LOCK string 1
7

        {

        }

    }
    PORT G1 output 
    {
        ATTR LOCK string 2
10

        {

        }

    }
    PORT Y2 output 
    {
        ATTR LOCK string 1
5

        {

        }

    }
    PORT Y1 output 
    {
        ATTR LOCK string 1
8

        {

        }

    }
    PORT R2 output 
    {
        ATTR LOCK string 1
6

        {

        }

    }
    PORT R1 output 
    {
        ATTR LOCK string 1
9

        {

        }

    }
    PORT B(3) output 
    {
        ATTR LOCK string 2
37

        {

        }

    }
    PORT B(2) output 
    {
        ATTR LOCK string 2
36

        {

        }

    }
    PORT B(1) output 
    {
        ATTR LOCK string 2
35

        {

        }

    }
    PORT B(0) output 
    {
        ATTR LOCK string 2
34

        {

        }

    }
    PORT A(3) output 
    {
        ATTR LOCK string 2
41

        {

        }

    }
    PORT A(2) output 
    {
        ATTR LOCK string 2
40

        {

        }

    }
    PORT A(1) output 
    {
        ATTR LOCK string 2
39

        {

        }

    }
    PORT A(0) output 
    {
        ATTR LOCK string 2
38

        {

        }

    }
    ATTR Y0_AS_EXCEPT bool 4 0
    {

    }
    ATTR BSCAN_EXCEPT_Y2 bool 4 0
    {

    }
    ATTR Y1_AS_RESET bool 4 0
    {

    }
    ATTR ISP_EXCEPT_Y2 bool 4 0
    {

    }
    ATTR ISP bool 4 1
    {

    }
    ATTR SECURITY bool 4 1
    {

    }
    ATTR VOLTAGE string 5
VCCIO

    {

    }
    ATTR OUTDELAY bool 4 0
    {

    }
    ATTR LOWPOWER bool 4 0
    {

    }
    ATTR TOE_AS_IO bool 4 0
    {

    }
    ATTR MAX_GLB_OUT int 4 4
    {

    }
    ATTR MAX_GLB_IN int 4 16
    {

    }
    ATTR CONFIGURATION string 13
CONFIG_HOLDER

    {
        ATTR $default string 1405
CFG_LST=$default
	VERSION=1.00
	OPTION=
	DEVICE=ispLSI1032E-70LJ84
	RESERVED_PINS=
	TIMING_ANALYSIS=0
	TA_MIN_DELAY=1
	TA_LSPATHS=1
	TA_MAX_PATHS=10
	TA_DEST_NODES=0
	TA_CLK_FREQ=ON
	TA_SETUP_HOLD=ON
	TA_CLK_TO_OUT=ON
	TA_TPD=ON
	TA_ENUM_PATHS=1
	TIMING_FILE=
	PARAMETER_FILE=
	USE_PARAMETER_FILE=OFF
	PERFORM_TA=ON
	PIN_FILE=
	PART_NAME=
	OUTPUT_FORM=
	EXTENDED_ROUTE=ON
	IGNORE_FIXED_PIN=OFF
	USE_GLOBAL_RESET=ON
	EXTENDED_LOGIC_OPT=OFF
	MIN_GLB=1
	CARRY_PIN_DIR=OFF
	CASE_SENSITIVE=OFF
	IGNORE_RESERVE_PIN=OFF
	SECURITY=ON
	ISP=ON
	ISP_EXCEPT_Y2=OFF
	Y1_AS_RESET=OFF
	PULLUP=ON
	SLOWSLEW=OFF
	OPENDRAIN=OFF
	PORT_LST
		A(0)	D=OUT	L=38	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		A(1)	D=OUT	L=39	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		A(2)	D=OUT	L=40	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		A(3)	D=OUT	L=41	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		B(0)	D=OUT	L=34	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		B(1)	D=OUT	L=35	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		B(2)	D=OUT	L=36	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		B(3)	D=OUT	L=37	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		G1	D=OUT	L=10	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		G2	D=OUT	L=7	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		R1	D=OUT	L=9	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		R2	D=OUT	L=6	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y1	D=OUT	L=8	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y2	D=OUT	L=5	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		clk	D=IN	L=20	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
	PORT_END

	OPTION_LST
		EFFORT=2
		STRATEGY=d
		MAX_GLB_IN=16
		MAX_GLB_OUT=4
	OPTION_END
CFG_END


        {

        }

    }
    ATTR PART string 18
ispLSI1032E-70LJ84

    {

    }
    ATTR TECHNOLOGY string 4
pLSI

    {

    }
    ATTR STAT string 30
edif2laf 1.0 23.9.2000 9.2.9 1

    {

    }
    ATTR DESIGN string 6
TRAFIC

    {

    }
    ATTR DESIGN_REV string 3
0.0

    {

    }

}