trafic.vhm

CPLD lattice1032 VHDL实现交通灯控制！

  II_N_116_I: INV port map (
      ZN0 => N_116_I,
      A0 => N_116);
  II_N_114_I: INV port map (
      ZN0 => N_114_I,
      A0 => N_114);
  II_N_115_I: INV port map (
      ZN0 => N_115_I,
      A0 => N_115);
  II_N_113_I: INV port map (
      ZN0 => N_113_I,
      A0 => N_113);
  \II_TEMP_I[3]\: INV port map (
      ZN0 => TEMP_I(3),
      A0 => TEMP(3));
  \II_TEMP_I[0]\: INV port map (
      ZN0 => TEMP_I(0),
      A0 => TEMP(0));
  \II_TEMP_I[1]\: INV port map (
      ZN0 => TEMP_I(1),
      A0 => TEMP(1));
  II_NUM_AND4_0_6_125: AND2 port map (
      Z0 => N_182,
      A0 => TEMP(3),
      A1 => TEMP(0));
  II_NUM_AND4_7_126: AND2 port map (
      Z0 => N_183,
      A0 => TEMP_I(1),
      A1 => TEMP(3));
  II_NUM_AND4_5_127: AND2 port map (
      Z0 => N_184,
      A0 => TEMP_I(3),
      A1 => TEMP_I(0));
  II_NUM_36_128: AND2 port map (
      Z0 => N_185,
      A0 => N_113_I,
      A1 => N_80_I);
  II_NUM_36_129: AND2 port map (
      Z0 => N_186,
      A0 => N_115_I,
      A1 => N_114_I);
  II_NUM_7_130: AND2 port map (
      Z0 => N_187,
      A0 => N_116_I,
      A1 => N_114_I);
  II_NUM_1_131: AND2 port map (
      Z0 => N_188,
      A0 => N_103_I,
      A1 => N_102_I);
  II_NUM_34_132: AND2 port map (
      Z0 => N_189,
      A0 => N_111_I,
      A1 => N_102_I);
  II_NUM_35_133: AND2 port map (
      Z0 => N_190,
      A0 => N_120_I,
      A1 => N_112_I);
  II_NUM_32_134: AND2 port map (
      Z0 => N_191,
      A0 => N_106_I,
      A1 => N_105_I);
  II_NUM_32_135: AND2 port map (
      Z0 => N_192,
      A0 => N_80_I,
      A1 => N_107_I);
  II_NUM_3_136: AND2 port map (
      Z0 => N_193,
      A0 => N_108_I,
      A1 => N_109_I);
  II_N_108_I: INV port map (
      ZN0 => N_108_I,
      A0 => N_108);
  II_N_109_I: INV port map (
      ZN0 => N_109_I,
      A0 => N_109);
  II_N_80_I: INV port map (
      ZN0 => N_80_I,
      A0 => N_80);
  II_NUM_36: AND2 port map (
      Z0 => N_145,
      A0 => N_185,
      A1 => N_186);
  \II_NUM[7]\: AND2 port map (
      Z0 => N_143,
      A0 => N_110_I,
      A1 => N_187);
  \II_NUM_AND4_0[3]\: AND2 port map (
      Z0 => N_109,
      A0 => TEMP_I(1),
      A1 => N_181);
  II_NUM_38_I_AND2: AND2 port map (
      Z0 => N_80,
      A0 => N_179,
      A1 => N_180);
  \II_NUM[1]\: AND2 port map (
      Z0 => N_141,
      A0 => N_104_I,
      A1 => N_188);
  \II__16\: AND2 port map (
      Z0 => N_25_I_0,
      A0 => N_19_I,
      A1 => N_177);
  \II_P2.UN2_COUNT0\: AND2 port map (
      Z0 => \P2.UN2_COUNT0\,
      A0 => \P2.UN2_COUNT0_1\,
      A1 => N_176);
  \II_P3.UN2_COUNT1\: AND2 port map (
      Z0 => \P3.UN2_COUNT1\,
      A0 => \P3.UN2_COUNT1_1\,
      A1 => N_175);
  \II_P3.UN2_COUNT1_118\: AND2 port map (
      Z0 => N_175,
      A0 => COUNT1_I(3),
      A1 => COUNT1_I(2));
  \II_P2.UN2_COUNT0_119\: AND2 port map (
      Z0 => N_176,
      A0 => COUNT0_I(3),
      A1 => COUNT0_I(2));
  \II__16_120\: AND2 port map (
      Z0 => N_177,
      A0 => COUNT1_I(2),
      A1 => \P3.UN2_COUNT1_1\);
  II_NUM_AND4_6_121: AND2 port map (
      Z0 => N_178,
      A0 => TEMP_I(0),
      A1 => TEMP(2));
  II_NUM_38_I_AND2_122: AND2 port map (
      Z0 => N_179,
      A0 => TEMP(1),
      A1 => TEMP(0));
  II_NUM_38_I_AND2_123: AND2 port map (
      Z0 => N_180,
      A0 => TEMP(3),
      A1 => TEMP(2));
  II_NUM_AND4_0_3_124: AND2 port map (
      Z0 => N_181,
      A0 => TEMP(0),
      A1 => TEMP_I(2));
  \II_NUM[3]\: AND2 port map (
      Z0 => N_155,
      A0 => N_107_I,
      A1 => N_193);
  II_NUM_32: AND2 port map (
      Z0 => NUM_C(2),
      A0 => N_191,
      A1 => N_192);
  II_NUM_35: AND2 port map (
      Z0 => N_150,
      A0 => N_80_I,
      A1 => N_190);
  II_NUM_34: AND2 port map (
      Z0 => N_148,
      A0 => N_110_I,
      A1 => N_189);
  \II_NUM_AND4[5]\: AND2 port map (
      Z0 => N_112,
      A0 => N_98_I_0,
      A1 => N_184);
  \II_NUM_AND4[6]\: AND2 port map (
      Z0 => N_113,
      A0 => N_97_I_0_I,
      A1 => N_178);
  \II_NUM_AND4_0[6]\: AND2 port map (
      Z0 => N_114,
      A0 => N_98_I_0,
      A1 => N_182);
  \II_NUM_AND4[7]\: AND2 port map (
      Z0 => N_116,
      A0 => N_118,
      A1 => N_183);
  II_UN1_LOAD_1: AND2 port map (
      Z0 => UN1_LOAD_1,
      A0 => LOAD,
      A1 => STATE_I(0));
  II_UN1_COUNTA: AND2 port map (
      Z0 => UN1_COUNTA,
      A0 => COUNTA(0),
      A1 => COUNTA(1));
  \II_P2.UN2_COUNT0_1\: AND2 port map (
      Z0 => \P2.UN2_COUNT0_1\,
      A0 => COUNT0_I(0),
      A1 => COUNT0_I(1));
  \II__8_97\: AND2 port map (
      Z0 => N_128_I,
      A0 => \P2.UN2_COUNT0_1\,
      A1 => \P2.UN3_COUNT0_I\);
  \II__8\: AND2 port map (
      Z0 => N_17_I_0,
      A0 => N_128_I,
      A1 => COUNT0_I(2));
  \II__5\: AND2 port map (
      Z0 => N_14,
      A0 => COUNT0(1),
      A1 => \P2.UN3_COUNT0_I\);
  \II_TEMP[3]\: MUX2 port map (
      Z0 => TEMP(3),
      A0 => COUNT0(3),
      A1 => COUNT1(3),
      S0 => COUNTA(0));
  \II_TEMP[2]\: MUX2 port map (
      Z0 => TEMP(2),
      A0 => COUNT0(2),
      A1 => COUNT1(2),
      S0 => COUNTA(0));
  \II_TEMP[1]\: MUX2 port map (
      Z0 => TEMP(1),
      A0 => COUNT0(1),
      A1 => COUNT1(1),
      S0 => COUNTA(0));
  \II_TEMP[0]\: MUX2 port map (
      Z0 => TEMP(0),
      A0 => COUNT0(0),
      A1 => COUNT1(0),
      S0 => COUNTA(0));
  \II__9\: MUX2 port map (
      Z0 => N_18,
      A0 => LOAD_I,
      A1 => COUNT0(3),
      S0 => \P2.UN3_COUNT0_I\);
  \II__7\: MUX2 port map (
      Z0 => N_16,
      A0 => UN1_LOAD_1,
      A1 => COUNT0(2),
      S0 => \P2.UN3_COUNT0_I\);
  \II__4\: AND2 port map (
      Z0 => N_13_I_0,
      A0 => COUNT0_I(0),
      A1 => \P2.UN3_COUNT0_I\);
  \II__3\: MUX2 port map (
      Z0 => N_12,
      A0 => LOAD_I,
      A1 => COUNT0(0),
      S0 => \P2.UN3_COUNT0_I\);
  II_UN9_SEL: AND2 port map (
      Z0 => UN9_SEL,
      A0 => COUNTA(1),
      A1 => COUNTA_I(0));
  II_UN3_SEL: AND2 port map (
      Z0 => UN3_SEL,
      A0 => COUNTA(0),
      A1 => COUNTA_I(1));
  II_UN1_SEL: AND2 port map (
      Z0 => UN1_SEL,
      A0 => COUNTA_I(0),
      A1 => COUNTA_I(1));
  II_COUNT1_E3: MUX2 port map (
      Z0 => COUNT1_E3,
      A0 => COUNT1(3),
      A1 => COUNT1_N3,
      S0 => EN);
  \II_STATE_0[1]\: MUX2 port map (
      Z0 => N_6,
      A0 => STATE_C(1),
      A1 => NEXT_STATE(1),
      S0 => \P4.UN22_COUNT0\);
  \II_P3.COUNT1_3_I_AND2[0]\: AND2 port map (
      Z0 => N_38,
      A0 => LOAD,
      A1 => \P6.LIGHT9_I\);
  \II__15\: AND2 port map (
      Z0 => N_24,
      A0 => N_19_I,
      A1 => COUNT1(2));
  \II_P3.UN2_COUNT1_1\: AND2 port map (
      Z0 => \P3.UN2_COUNT1_1\,
      A0 => COUNT1_I(0),
      A1 => COUNT1_I(1));
  II_COUNT1_N0: XOR2 port map (
      Z0 => COUNT1_N0,
      A0 => N_19_I,
      A1 => N_20);
  II_COUNT1_N1: XOR2 port map (
      Z0 => COUNT1_N1,
      A0 => N_21_I_0,
      A1 => N_22);
  II_COUNT1_N2: XOR2 port map (
      Z0 => COUNT1_N2,
      A0 => N_23_I_0,
      A1 => N_24);
  II_COUNT1_N3: XOR2 port map (
      Z0 => COUNT1_N3,
      A0 => N_25_I_0,
      A1 => N_26);
  \II_STATE_0[0]\: XOR2 port map (
      Z0 => N_5,
      A0 => \P4.UN22_COUNT0\,
      A1 => STATE(0));
  II_NEXT_STATE_1_2: XOR2 port map (
      Z0 => NEXT_STATE(1),
      A0 => STATE_C(1),
      A1 => STATE_I(0));
  II_COUNT0_N3: XOR2 port map (
      Z0 => COUNT0_N3,
      A0 => N_17_I_0,
      A1 => N_18);
  II_COUNT0_N2: XOR2 port map (
      Z0 => COUNT0_N2,
      A0 => N_16,
      A1 => N_128_I);
  II_COUNT0_N1: XOR2 port map (
      Z0 => COUNT0_N1,
      A0 => N_13_I_0,
      A1 => N_14);
  II_COUNT0_N0: XOR2 port map (
      Z0 => COUNT0_N0,
      A0 => N_12,
      A1 => \P2.UN3_COUNT0_I\);
  \II_P6.LIGHT10\: AND2 port map (
      Z0 => \P6.LIGHT10\,
      A0 => STATE_C(1),
      A1 => STATE_I(0));
  \II_P6.LIGHT11\: AND2 port map (
      Z0 => \P6.LIGHT11\,
      A0 => STATE(0),
      A1 => STATE_C_I(1));
  \II_P6.LIGHT12\: AND2 port map (
      Z0 => \P6.LIGHT12\,
      A0 => STATE_C_I(1),
      A1 => STATE_I(0));
  II_UN1_LOAD_3: AND2 port map (
      Z0 => UN1_LOAD_3,
      A0 => LOAD,
      A1 => STATE(0));
  \II_P2.UN3_COUNT0\: AND2 port map (
      Z0 => \P2.UN3_COUNT0_I\,
      A0 => LOAD_I,
      A1 => \P2.UN2_COUNT0_I\);
  \II_P3.UN3_COUNT1\: AND2 port map (
      Z0 => N_19_I,
      A0 => LOAD_I,
      A1 => \P3.UN2_COUNT1_I\);
  \II_P4.UN22_COUNT0\: AND2 port map (
      Z0 => \P4.UN22_COUNT0\,
      A0 => \P2.UN2_COUNT0\,
      A1 => \P3.UN2_COUNT1\);
  \II__11\: MUX2 port map (
      Z0 => N_20,
      A0 => N_38_I,
      A1 => COUNT1(0),
      S0 => N_19_I);
  II_COUNT1_E0: MUX2 port map (
      Z0 => COUNT1_E0,
      A0 => COUNT1(0),
      A1 => COUNT1_N0,
      S0 => EN);
  \II__12\: AND2 port map (
      Z0 => N_21_I_0,
      A0 => N_19_I,
      A1 => COUNT1_I(0));
  \II__13\: MUX2 port map (
      Z0 => N_22,
      A0 => UN1_LOAD_3,
      A1 => COUNT1(1),
      S0 => N_19_I);
  II_COUNT1_E1: MUX2 port map (
      Z0 => COUNT1_E1,
      A0 => COUNT1(1),
      A1 => COUNT1_N1,
      S0 => EN);
  \II__14\: AND2 port map (
      Z0 => N_23_I_0,
      A0 => N_19_I,
      A1 => \P3.UN2_COUNT1_1\);
  II_COUNT1_E2: MUX2 port map (
      Z0 => COUNT1_E2,
      A0 => COUNT1(2),
      A1 => COUNT1_N2,
      S0 => EN);
  \II__17\: MUX2 port map (
      Z0 => N_26,
      A0 => LOAD_I,
      A1 => COUNT1(3),
      S0 => N_19_I);
  \II_NUM_AND4[4]\: AND2 port map (
      Z0 => N_110,
      A0 => N_96_I,
      A1 => N_97_I_0);
  \II_NUM_AND4_0[4]\: AND2 port map (
      Z0 => N_111,
      A0 => N_98_I_0,
      A1 => N_119);
  \II_NUM_AND4_1[6]\: AND2 port map (
      Z0 => N_115,
      A0 => N_97_I_0,
      A1 => N_118);
  II_NUM_31: AND2 port map (
      Z0 => NUM_C(1),
      A0 => N_80_I,
      A1 => N_141_I);
  \II_P11.UN10_COUNT_1\: AND2 port map (
      Z0 => COUNT_C1,
      A0 => COUNT(0),
      A1 => COUNT(1));
  \II_P11.UN10_COUNT\: AND2 port map (
      Z0 => \P11.UN10_COUNT\,
      A0 => COUNT(2),
      A1 => COUNT_C1);
  II_COUNT_N1: XOR2 port map (
      Z0 => COUNT_N1,
      A0 => COUNT(0),
      A1 => COUNT(1));
  II_COUNT_N2: XOR2 port map (
      Z0 => COUNT_N2,
      A0 => COUNT(2),
      A1 => COUNT_C1);
  II_NUM_85: XOR2 port map (
      Z0 => N_96,
      A0 => TEMP(2),
      A1 => TEMP_I(0));
  \II_P6.LIGHT9\: AND2 port map (
      Z0 => \P6.LIGHT9\,
      A0 => STATE(0),
      A1 => STATE_C(1));
  II_NUM_82: AND2 port map (
      Z0 => N_118,
      A0 => TEMP(0),
      A1 => TEMP(2));
  II_NUM_83: AND2 port map (
      Z0 => N_119,
      A0 => TEMP(3),
      A1 => TEMP_I(0));
  II_NUM_84: AND2 port map (
      Z0 => N_120,
      A0 => N_119,
      A1 => TEMP(2));
  II_NUM_86: AND2 port map (
      Z0 => N_97_I_0,
      A0 => TEMP_I(1),
      A1 => TEMP_I(3));
  II_NUM_87: AND2 port map (
      Z0 => N_98_I_0,
      A0 => TEMP(1),
      A1 => TEMP_I(2));
  \II_NUM_AND4[1]\: AND2 port map (
      Z0 => N_102,
      A0 => N_118,
      A1 => TEMP(1));
  \II_NUM_AND4_0[1]\: AND2 port map (
      Z0 => N_103,
      A0 => N_97_I_0,
      A1 => TEMP_I(2));
  \II_NUM_AND4_1[1]\: AND2 port map (
      Z0 => N_104,
      A0 => N_120,
      A1 => TEMP_I(1));
  \II_NUM_I_AND4[2]\: AND2 port map (
      Z0 => N_105,
      A0 => N_98_I_0_I,
      A1 => TEMP_I(0));
  \II_NUM_I_AND4_0[2]\: AND2 port map (
      Z0 => N_106,
      A0 => TEMP(3),
      A1 => TEMP_I(2));
  \II_NUM_I_AND4_1[2]\: AND2 port map (
      Z0 => N_107,
      A0 => N_97_I_0,
      A1 => TEMP(2));
  \II_NUM_AND4[3]\: AND2 port map (
      Z0 => N_108,
      A0 => TEMP(0),
      A1 => TEMP_I(3));
  II_EN: LD11 port map (
      Q0 => EN,
      D0 => \P2.UN2_COUNT0\,
      G => CARRY_I);
  GND <= '0';
end beh;