trafic.vhm

CPLD lattice1032 VHDL实现交通灯控制！

  signal COUNT_I : std_logic_vector(0 to 0);
  signal CARRY : std_logic ;
  signal LOAD : std_logic ;
  signal UN1_COUNTA : std_logic ;
  signal \P11.UN10_COUNT\ : std_logic ;
  signal \P6.LIGHT9\ : std_logic ;
  signal \P6.LIGHT10\ : std_logic ;
  signal \P6.LIGHT11\ : std_logic ;
  signal \P6.LIGHT12\ : std_logic ;
  signal UN1_SEL : std_logic ;
  signal UN3_SEL : std_logic ;
  signal UN9_SEL : std_logic ;
  signal \P2.UN2_COUNT0\ : std_logic ;
  signal EN : std_logic ;
  signal \P4.UN22_COUNT0\ : std_logic ;
  signal N_5 : std_logic ;
  signal N_6 : std_logic ;
  signal COUNT_N1 : std_logic ;
  signal COUNT_N2 : std_logic ;
  signal COUNT0_N0 : std_logic ;
  signal COUNT0_N1 : std_logic ;
  signal COUNT0_N2 : std_logic ;
  signal COUNT0_N3 : std_logic ;
  signal COUNT1_E0 : std_logic ;
  signal COUNT1_E1 : std_logic ;
  signal COUNT1_E2 : std_logic ;
  signal COUNT1_E3 : std_logic ;
  signal N_80 : std_logic ;
  signal N_96 : std_logic ;
  signal N_102 : std_logic ;
  signal N_103 : std_logic ;
  signal N_104 : std_logic ;
  signal N_105 : std_logic ;
  signal N_106 : std_logic ;
  signal N_107 : std_logic ;
  signal N_108 : std_logic ;
  signal N_109 : std_logic ;
  signal N_110 : std_logic ;
  signal N_111 : std_logic ;
  signal N_112 : std_logic ;
  signal N_113 : std_logic ;
  signal N_114 : std_logic ;
  signal N_115 : std_logic ;
  signal N_116 : std_logic ;
  signal N_118 : std_logic ;
  signal N_119 : std_logic ;
  signal N_120 : std_logic ;
  signal N_123 : std_logic ;
  signal COUNT_C1 : std_logic ;
  signal UN1_LOAD_1 : std_logic ;
  signal N_12 : std_logic ;
  signal N_14 : std_logic ;
  signal N_16 : std_logic ;
  signal N_18 : std_logic ;
  signal \P2.UN2_COUNT0_1\ : std_logic ;
  signal N_24 : std_logic ;
  signal COUNT1_N3 : std_logic ;
  signal N_26 : std_logic ;
  signal COUNT1_N2 : std_logic ;
  signal \P3.UN2_COUNT1_1\ : std_logic ;
  signal COUNT1_N1 : std_logic ;
  signal N_22 : std_logic ;
  signal COUNT1_N0 : std_logic ;
  signal N_38 : std_logic ;
  signal N_20 : std_logic ;
  signal \P3.UN2_COUNT1\ : std_logic ;
  signal UN1_LOAD_3 : std_logic ;
  signal CLK_C : std_logic ;
  signal CLK1_C : std_logic ;
  signal VCC : std_logic ;
  signal N_141 : std_logic ;
  signal N_143 : std_logic ;
  signal N_145 : std_logic ;
  signal N_148 : std_logic ;
  signal N_150 : std_logic ;
  signal N_155 : std_logic ;
  signal \P2.UN3_COUNT0_I\ : std_logic ;
  signal N_13_I_0 : std_logic ;
  signal N_128_I : std_logic ;
  signal N_17_I_0 : std_logic ;
  signal N_25_I_0 : std_logic ;
  signal N_23_I_0 : std_logic ;
  signal N_21_I_0 : std_logic ;
  signal N_19_I : std_logic ;
  signal N_98_I_0 : std_logic ;
  signal N_97_I_0 : std_logic ;
  signal N_175 : std_logic ;
  signal N_176 : std_logic ;
  signal N_177 : std_logic ;
  signal N_178 : std_logic ;
  signal N_179 : std_logic ;
  signal N_180 : std_logic ;
  signal N_181 : std_logic ;
  signal N_182 : std_logic ;
  signal N_183 : std_logic ;
  signal N_184 : std_logic ;
  signal N_185 : std_logic ;
  signal N_186 : std_logic ;
  signal N_187 : std_logic ;
  signal N_188 : std_logic ;
  signal N_189 : std_logic ;
  signal N_190 : std_logic ;
  signal N_191 : std_logic ;
  signal N_192 : std_logic ;
  signal N_193 : std_logic ;
  signal N_108_I : std_logic ;
  signal N_109_I : std_logic ;
  signal N_80_I : std_logic ;
  signal N_107_I : std_logic ;
  signal N_106_I : std_logic ;
  signal N_105_I : std_logic ;
  signal N_120_I : std_logic ;
  signal N_112_I : std_logic ;
  signal N_111_I : std_logic ;
  signal N_102_I : std_logic ;
  signal N_103_I : std_logic ;
  signal N_116_I : std_logic ;
  signal N_114_I : std_logic ;
  signal N_115_I : std_logic ;
  signal N_113_I : std_logic ;
  signal N_104_I : std_logic ;
  signal N_110_I : std_logic ;
  signal N_97_I_0_I : std_logic ;
  signal UN1_COUNTA_I : std_logic ;
  signal UN9_SEL_I : std_logic ;
  signal UN3_SEL_I : std_logic ;
  signal UN1_SEL_I : std_logic ;
  signal N_143_I : std_logic ;
  signal N_145_I : std_logic ;
  signal N_150_I : std_logic ;
  signal N_148_I : std_logic ;
  signal N_155_I : std_logic ;
  signal \P6.LIGHT11_I\ : std_logic ;
  signal \P6.LIGHT9_I\ : std_logic ;
  signal \P6.LIGHT12_I\ : std_logic ;
  signal \P6.LIGHT10_I\ : std_logic ;
  signal LOAD_I : std_logic ;
  signal N_38_I : std_logic ;
  signal \P3.UN2_COUNT1_I\ : std_logic ;
  signal \P2.UN2_COUNT0_I\ : std_logic ;
  signal N_141_I : std_logic ;
  signal N_96_I : std_logic ;
  signal N_98_I_0_I : std_logic ;
  signal CARRY_I : std_logic ;
  signal GND : std_logic ;
  component FD11
    port(
      Q0 :  out std_logic;
      D0 :  in std_logic;
      CLK :  in std_logic  );
  end component;
  component XOR2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic  );
  end component;
  component AND2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic  );
  end component;
  component IB11
    port(
      Z0 :  out std_logic;
      XI0 :  in std_logic  );
  end component;
  component OB11
    port(
      XO0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
  component INV
    port(
      ZN0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
  component MUX2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic;
      S0 :  in std_logic  );
  end component;
  component LD11
    port(
      Q0 :  out std_logic;
      D0 :  in std_logic;
      G :  in std_logic  );
  end component;
begin
  \II_COUNTA[1]\: FD11 port map (
      Q0 => COUNTA(1),
      D0 => UN6_COUNTA(1),
      CLK => CLK1_C);
  \II_STATE[0]\: FD11 port map (
      Q0 => STATE(0),
      D0 => N_5,
      CLK => CARRY_I);
  \II_STATE[1]\: FD11 port map (
      Q0 => STATE_C(1),
      D0 => N_6,
      CLK => CARRY_I);
  \II_COUNT1[1]\: FD11 port map (
      Q0 => COUNT1(1),
      D0 => COUNT1_E1,
      CLK => CARRY);
  \II_COUNT1[2]\: FD11 port map (
      Q0 => COUNT1(2),
      D0 => COUNT1_E2,
      CLK => CARRY);
  \II_COUNT1[3]\: FD11 port map (
      Q0 => COUNT1(3),
      D0 => COUNT1_E3,
      CLK => CARRY);
  \II_COUNTA[0]\: FD11 port map (
      Q0 => COUNTA(0),
      D0 => UN6_COUNTA(2),
      CLK => CLK1_C);
  \II_COUNT0[3]\: FD11 port map (
      Q0 => COUNT0(3),
      D0 => COUNT0_N3,
      CLK => CARRY);
  \II_COUNT1[0]\: FD11 port map (
      Q0 => COUNT1(0),
      D0 => COUNT1_E0,
      CLK => CARRY);
  \II_COUNT0[1]\: FD11 port map (
      Q0 => COUNT0(1),
      D0 => COUNT0_N1,
      CLK => CARRY);
  \II_COUNT0[2]\: FD11 port map (
      Q0 => COUNT0(2),
      D0 => COUNT0_N2,
      CLK => CARRY);
  \II_COUNT[0]\: FD11 port map (
      Q0 => COUNT(0),
      D0 => COUNT_I(0),
      CLK => CLK_C);
  \II_COUNT[1]\: FD11 port map (
      Q0 => COUNT(1),
      D0 => COUNT_N1,
      CLK => CLK_C);
  \II_COUNT[2]\: FD11 port map (
      Q0 => COUNT(2),
      D0 => COUNT_N2,
      CLK => CLK_C);
  \II_COUNT0[0]\: FD11 port map (
      Q0 => COUNT0(0),
      D0 => COUNT0_N0,
      CLK => CARRY);
  II_LOAD: FD11 port map (
      Q0 => LOAD,
      D0 => \P4.UN22_COUNT0\,
      CLK => CARRY_I);
  II_CARRY: FD11 port map (
      Q0 => CARRY,
      D0 => \P11.UN10_COUNT\,
      CLK => CLK_C);
  II_I_91: XOR2 port map (
      Z0 => UN6_COUNTA(2),
      A0 => COUNTA(0),
      A1 => VCC);
  II_I_92: AND2 port map (
      Z0 => N_123,
      A0 => COUNTA(0),
      A1 => VCC);
  II_I_93: XOR2 port map (
      Z0 => UN6_COUNTA(1),
      A0 => COUNTA(1),
      A1 => N_123);
  VCC <= '1';
  II_CLK: IB11 port map (
      Z0 => CLK_C,
      XI0 => clk);
  II_CLK1: IB11 port map (
      Z0 => CLK1_C,
      XI0 => clk1);
  II_R1: OB11 port map (
      XO0 => R1,
      A0 => STATE_C(1));
  II_R2: OB11 port map (
      XO0 => R2,
      A0 => STATE_C_I(1));
  II_Y1: OB11 port map (
      XO0 => Y1,
      A0 => \P6.LIGHT10_I\);
  II_Y2: OB11 port map (
      XO0 => Y2,
      A0 => \P6.LIGHT12_I\);
  II_G1: OB11 port map (
      XO0 => G1,
      A0 => \P6.LIGHT9_I\);
  II_G2: OB11 port map (
      XO0 => G2,
      A0 => \P6.LIGHT11_I\);
  \II_SEGOUT[0]\: OB11 port map (
      XO0 => segout(0),
      A0 => VCC);
  \II_SEGOUT[1]\: OB11 port map (
      XO0 => segout(1),
      A0 => NUM_C(1));
  \II_SEGOUT[2]\: OB11 port map (
      XO0 => segout(2),
      A0 => NUM_C(2));
  \II_SEGOUT[3]\: OB11 port map (
      XO0 => segout(3),
      A0 => N_155_I);
  \II_SEGOUT[4]\: OB11 port map (
      XO0 => segout(4),
      A0 => N_148_I);
  \II_SEGOUT[5]\: OB11 port map (
      XO0 => segout(5),
      A0 => N_150_I);
  \II_SEGOUT[6]\: OB11 port map (
      XO0 => segout(6),
      A0 => N_145_I);
  \II_SEGOUT[7]\: OB11 port map (
      XO0 => segout(7),
      A0 => N_143_I);
  \II_SELOUT[0]\: OB11 port map (
      XO0 => selout(0),
      A0 => UN1_SEL_I);
  \II_SELOUT[1]\: OB11 port map (
      XO0 => selout(1),
      A0 => UN3_SEL_I);
  \II_SELOUT[2]\: OB11 port map (
      XO0 => selout(2),
      A0 => UN9_SEL_I);
  \II_SELOUT[3]\: OB11 port map (
      XO0 => selout(3),
      A0 => UN1_COUNTA_I);
  \II_P3.N_38_I\: INV port map (
      ZN0 => N_38_I,
      A0 => N_38);
  \II_P3.UN2_COUNT1_I\: INV port map (
      ZN0 => \P3.UN2_COUNT1_I\,
      A0 => \P3.UN2_COUNT1\);
  \II_P2.UN2_COUNT0_I\: INV port map (
      ZN0 => \P2.UN2_COUNT0_I\,
      A0 => \P2.UN2_COUNT0\);
  II_N_141_I: INV port map (
      ZN0 => N_141_I,
      A0 => N_141);
  II_N_96_I: INV port map (
      ZN0 => N_96_I,
      A0 => N_96);
  II_N_98_I_0_I: INV port map (
      ZN0 => N_98_I_0_I,
      A0 => N_98_I_0);
  II_CARRY_I: INV port map (
      ZN0 => CARRY_I,
      A0 => CARRY);
  \II_COUNT_I[0]\: INV port map (
      ZN0 => COUNT_I(0),
      A0 => COUNT(0));
  II_N_148_I: INV port map (
      ZN0 => N_148_I,
      A0 => N_148);
  II_N_155_I: INV port map (
      ZN0 => N_155_I,
      A0 => N_155);
  \II_P6.LIGHT11_I\: INV port map (
      ZN0 => \P6.LIGHT11_I\,
      A0 => \P6.LIGHT11\);
  \II_P6.LIGHT9_I\: INV port map (
      ZN0 => \P6.LIGHT9_I\,
      A0 => \P6.LIGHT9\);
  \II_P6.LIGHT12_I\: INV port map (
      ZN0 => \P6.LIGHT12_I\,
      A0 => \P6.LIGHT12\);
  \II_P6.LIGHT10_I\: INV port map (
      ZN0 => \P6.LIGHT10_I\,
      A0 => \P6.LIGHT10\);
  \II_STATE_C_I[1]\: INV port map (
      ZN0 => STATE_C_I(1),
      A0 => STATE_C(1));
  \II_STATE_I[0]\: INV port map (
      ZN0 => STATE_I(0),
      A0 => STATE(0));
  \II_COUNTA_I[0]\: INV port map (
      ZN0 => COUNTA_I(0),
      A0 => COUNTA(0));
  \II_COUNTA_I[1]\: INV port map (
      ZN0 => COUNTA_I(1),
      A0 => COUNTA(1));
  II_LOAD_I: INV port map (
      ZN0 => LOAD_I,
      A0 => LOAD);
  \II_COUNT0_I[0]\: INV port map (
      ZN0 => COUNT0_I(0),
      A0 => COUNT0(0));
  \II_COUNT0_I[1]\: INV port map (
      ZN0 => COUNT0_I(1),
      A0 => COUNT0(1));
  \II_COUNT1_I[0]\: INV port map (
      ZN0 => COUNT1_I(0),
      A0 => COUNT1(0));
  \II_COUNT1_I[1]\: INV port map (
      ZN0 => COUNT1_I(1),
      A0 => COUNT1(1));
  \II_TEMP_I[2]\: INV port map (
      ZN0 => TEMP_I(2),
      A0 => TEMP(2));
  \II_COUNT1_I[2]\: INV port map (
      ZN0 => COUNT1_I(2),
      A0 => COUNT1(2));
  \II_COUNT0_I[3]\: INV port map (
      ZN0 => COUNT0_I(3),
      A0 => COUNT0(3));
  \II_COUNT0_I[2]\: INV port map (
      ZN0 => COUNT0_I(2),
      A0 => COUNT0(2));
  \II_COUNT1_I[3]\: INV port map (
      ZN0 => COUNT1_I(3),
      A0 => COUNT1(3));
  II_N_104_I: INV port map (
      ZN0 => N_104_I,
      A0 => N_104);
  II_N_110_I: INV port map (
      ZN0 => N_110_I,
      A0 => N_110);
  II_N_97_I_0_I: INV port map (
      ZN0 => N_97_I_0_I,
      A0 => N_97_I_0);
  II_UN1_COUNTA_I: INV port map (
      ZN0 => UN1_COUNTA_I,
      A0 => UN1_COUNTA);
  II_UN9_SEL_I: INV port map (
      ZN0 => UN9_SEL_I,
      A0 => UN9_SEL);
  II_UN3_SEL_I: INV port map (
      ZN0 => UN3_SEL_I,
      A0 => UN3_SEL);
  II_UN1_SEL_I: INV port map (
      ZN0 => UN1_SEL_I,
      A0 => UN1_SEL);
  II_N_143_I: INV port map (
      ZN0 => N_143_I,
      A0 => N_143);
  II_N_145_I: INV port map (
      ZN0 => N_145_I,
      A0 => N_145);
  II_N_150_I: INV port map (
      ZN0 => N_150_I,
      A0 => N_150);
  II_N_107_I: INV port map (
      ZN0 => N_107_I,
      A0 => N_107);
  II_N_106_I: INV port map (
      ZN0 => N_106_I,
      A0 => N_106);
  II_N_105_I: INV port map (
      ZN0 => N_105_I,
      A0 => N_105);
  II_N_120_I: INV port map (
      ZN0 => N_120_I,
      A0 => N_120);
  II_N_112_I: INV port map (
      ZN0 => N_112_I,
      A0 => N_112);
  II_N_111_I: INV port map (
      ZN0 => N_111_I,
      A0 => N_111);
  II_N_102_I: INV port map (
      ZN0 => N_102_I,
      A0 => N_102);
  II_N_103_I: INV port map (
      ZN0 => N_103_I,
      A0 => N_103);