trafic.vhm

CPLD lattice1032 VHDL实现交通灯控制！

--
-- Written by Synplicity
-- Thu Dec 06 09:08:46 2007
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity XINPUT is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end XINPUT;

architecture beh of XINPUT is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  Z0 <= XI0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity XOUTPUT is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end XOUTPUT;

architecture beh of XOUTPUT is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  XO0 <= A0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DFF_FD is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CP :  in std_logic;
  R :  in std_logic);
end DFF_FD;

architecture beh of DFF_FD is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  II_Q: prim_dff port map (Q, D, CP, R, '0');
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BUF is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic);
end BUF;

architecture beh of BUF is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  Z0 <= A0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OR3 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  A2 :  in std_logic);
end OR3;

architecture beh of OR3 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  Z0 <= A0 or A1 or A2  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  Z0 <= A0 or A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  Z0 <= A0 and A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  ZN0 :  out std_logic;
  A0 :  in std_logic);
end INV;

architecture beh of INV is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  ZN0 <= not A0;
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IB11 is
port(
  Z0 :  out std_logic;
  XI0 :  in std_logic);
end IB11;

architecture beh of IB11 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component XINPUT
    port(
      Z0 :  out std_logic;
      XI0 :  in std_logic  );
  end component;
begin
  \II_$1I45\: XINPUT port map (
      Z0 => Z0,
      XI0 => XI0);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity LD11 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  G :  in std_logic);
end LD11;

architecture beh of LD11 is
  signal \$1N261\ : std_logic ;
  signal \$1N188\ : std_logic ;
  signal \$1N166\ : std_logic ;
  signal \$1N159\ : std_logic ;
  signal \$1N6\ : std_logic ;
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component OR3
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic;
      A2 :  in std_logic  );
  end component;
  component AND2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic  );
  end component;
  component INV
    port(
      ZN0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
  component BUF
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
begin
  \II_$1I186\: OR3 port map (
      Z0 => \$1N6\,
      A0 => \$1N166\,
      A1 => \$1N159\,
      A2 => \$1N188\);
  \II_$1I254\: AND2 port map (
      Z0 => \$1N166\,
      A0 => \$1N6\,
      A1 => D0);
  \II_$1I257\: AND2 port map (
      Z0 => \$1N188\,
      A0 => D0,
      A1 => G);
  \II_$1I258\: AND2 port map (
      Z0 => \$1N159\,
      A0 => \$1N6\,
      A1 => \$1N261\);
  \II_$1I260\: INV port map (
      ZN0 => \$1N261\,
      A0 => G);
  \II_$1I270\: BUF port map (
      Z0 => Q0,
      A0 => \$1N6\);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity MUX2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic;
  S0 :  in std_logic);
end MUX2;

architecture beh of MUX2 is
  signal \$1N8\ : std_logic ;
  signal \$1N22\ : std_logic ;
  signal \$1N6\ : std_logic ;
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component AND2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic  );
  end component;
  component OR2
    port(
      Z0 :  out std_logic;
      A0 :  in std_logic;
      A1 :  in std_logic  );
  end component;
  component INV
    port(
      ZN0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
begin
  \II_$1I25\: AND2 port map (
      Z0 => \$1N6\,
      A0 => A0,
      A1 => \$1N22\);
  \II_$1I31\: AND2 port map (
      Z0 => \$1N8\,
      A0 => A1,
      A1 => S0);
  \II_$1I35\: OR2 port map (
      Z0 => Z0,
      A0 => \$1N6\,
      A1 => \$1N8\);
  \II_$1I38\: INV port map (
      ZN0 => \$1N22\,
      A0 => S0);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OB11 is
port(
  XO0 :  out std_logic;
  A0 :  in std_logic);
end OB11;

architecture beh of OB11 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component XOUTPUT
    port(
      XO0 :  out std_logic;
      A0 :  in std_logic  );
  end component;
begin
  \II_$1I42\: XOUTPUT port map (
      XO0 => XO0,
      A0 => A0);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD11 is
port(
  Q0 :  out std_logic;
  D0 :  in std_logic;
  CLK :  in std_logic);
end FD11;

architecture beh of FD11 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
  component DFF_FD
    port(
      Q :  out std_logic;
      D :  in std_logic;
      CP :  in std_logic;
      R :  in std_logic  );
  end component;
begin
  II_BLK2: DFF_FD port map (
      Q => Q0,
      D => D0,
      CP => CLK,
      R => GND);
  VCC <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity XOR2 is
port(
  Z0 :  out std_logic;
  A0 :  in std_logic;
  A1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal VCC : std_logic ;
  signal GND : std_logic ;
begin
  VCC <= '1';
  GND <= '0';
  Z0 <= A0 xor A1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity trafic is
port(
  clk :  in std_logic;
  clk1 :  in std_logic;
  R1 :  out std_logic;
  R2 :  out std_logic;
  Y1 :  out std_logic;
  Y2 :  out std_logic;
  G1 :  out std_logic;
  G2 :  out std_logic;
  segout : out std_logic_vector(7 downto 0);
  selout : out std_logic_vector(3 downto 0));
end trafic;

architecture beh of trafic is
  signal COUNTA : std_logic_vector(1 downto 0);
  signal COUNT0 : std_logic_vector(3 downto 0);
  signal COUNT1 : std_logic_vector(3 downto 0);
  signal STATE : std_logic_vector(0 to 0);
  signal COUNT : std_logic_vector(2 downto 0);
  signal TEMP : std_logic_vector(3 downto 0);
  signal UN6_COUNTA : std_logic_vector(2 downto 1);
  signal NEXT_STATE : std_logic_vector(1 to 1);
  signal STATE_C : std_logic_vector(1 to 1);
  signal NUM_C : std_logic_vector(2 downto 1);
  signal TEMP_I : std_logic_vector(3 downto 0);
  signal COUNT1_I : std_logic_vector(3 downto 0);
  signal COUNT0_I : std_logic_vector(3 downto 0);
  signal STATE_C_I : std_logic_vector(1 to 1);
  signal STATE_I : std_logic_vector(0 to 0);
  signal COUNTA_I : std_logic_vector(1 downto 0);