trafic.tlg

CPLD lattice1032 VHDL实现交通灯控制！

Synthesizing work.trafic.arch
@N:"E:\EDAPRO~2\pt1032e\trafic\trafic.vhd":15:12:15:13|Using sequential encoding for type states
Post processing for work.trafic.arch
@W:"E:\EDAPRO~2\pt1032e\trafic\trafic.vhd":80:2:80:3|Latch generated from process for signal en, probably caused by a missing assignment in an if or case stmt
@N:"E:\EDAPRO~2\pt1032e\trafic\trafic.vhd":104:3:104:4|Trying to extract state machine for register state