trafic.vto

CPLD lattice1032 VHDL实现交通灯控制！

GLB_D5_IN3B : PGINVI
	PORT MAP (ZN0 => D5_IN3B, A0 => UQNNONMCK_117);
GLB_D5_IN6B : PGINVI
	PORT MAP (ZN0 => D5_IN6B, A0 => UQNNONMCK_114);
GLB_D5_IN1B : PGINVI
	PORT MAP (ZN0 => D5_IN1B, A0 => UQNNONMCK_118);
GLB_D5_IN4B : PGINVI
	PORT MAP (ZN0 => D5_IN4B, A0 => UQNNONMCK_119);
GLB_D5_IN9B : PGINVI
	PORT MAP (ZN0 => D5_IN9B, A0 => UQNNONMCK_113);
GLB_D5_IN7B : PGINVI
	PORT MAP (ZN0 => D5_IN7B, A0 => UQNNONMCK_115);
GLB_D5_IN2B : PGINVI
	PORT MAP (ZN0 => D5_IN2B, A0 => UQNNONMCK_121);
GLB_D6_P7 : PGAND4
	PORT MAP (Z0 => D6_P7, A3 => D6_IN2B, A2 => D6_IN5B, A1 => D6_IN6, 
	A0 => D6_IN7B);
GLB_D6_P6 : PGAND4
	PORT MAP (Z0 => D6_P6, A3 => D6_IN2B, A2 => D6_IN5B, A1 => D6_IN7B, 
	A0 => D6_IN9);
GLB_D6_P5 : PGAND5
	PORT MAP (Z0 => D6_P5, A4 => D6_IN0, A3 => D6_IN1B, A2 => D6_IN2, 
	A1 => D6_IN3, A0 => D6_IN4);
GLB_D6_P4 : PGAND5
	PORT MAP (Z0 => D6_P4, A4 => D6_IN2B, A3 => D6_IN5, A2 => D6_IN6, 
	A1 => D6_IN7, A0 => D6_IN9B);
GLB_D6_P3 : PGAND4
	PORT MAP (Z0 => D6_P3, A3 => D6_IN0B, A2 => D6_IN1, A1 => D6_IN2, 
	A0 => D6_IN3);
GLB_D6_P2 : PGAND4
	PORT MAP (Z0 => D6_P2, A3 => D6_IN0B, A2 => D6_IN2, A1 => D6_IN3, 
	A0 => D6_IN4B);
GLB_D6_P1 : PGAND4
	PORT MAP (Z0 => D6_P1, A3 => D6_IN0B, A2 => D6_IN1, A1 => D6_IN2, 
	A0 => D6_IN4B);
GLB_D6_P0 : PGAND4
	PORT MAP (Z0 => D6_P0, A3 => D6_IN2B, A2 => D6_IN5B, A1 => D6_IN6, 
	A0 => D6_IN9);
GLB_D6_G2 : PGORF72
	PORT MAP (Z0 => D6_G2, A1 => D6_F0, A0 => D6_F1);
GLB_D6_F1 : PGORF74
	PORT MAP (Z0 => D6_F1, A3 => D6_P4, A2 => D6_P5, A1 => D6_P6, 
	A0 => D6_P7);
GLB_D6_F0 : PGORF74
	PORT MAP (Z0 => D6_F0, A3 => D6_P0, A2 => D6_P1, A1 => D6_P2, 
	A0 => D6_P3);
GLB_OR_759 : PGBUFI
	PORT MAP (Z0 => OR_759, A0 => D6_X1O);
GLB_D6_IN4 : PGBUFI
	PORT MAP (Z0 => D6_IN4, A0 => UQNNONMCK_119);
GLB_D6_IN0 : PGBUFI
	PORT MAP (Z0 => D6_IN0, A0 => UQNNONMCK_120);
GLB_D6_IN7 : PGBUFI
	PORT MAP (Z0 => D6_IN7, A0 => UQNNONMCK_115);
GLB_D6_IN5 : PGBUFI
	PORT MAP (Z0 => D6_IN5, A0 => UQNNONMCK_116);
GLB_D6_IN3 : PGBUFI
	PORT MAP (Z0 => D6_IN3, A0 => UQNNONMCK_117);
GLB_D6_IN2 : PGBUFI
	PORT MAP (Z0 => D6_IN2, A0 => UQNNONMCK_121);
GLB_D6_IN1 : PGBUFI
	PORT MAP (Z0 => D6_IN1, A0 => UQNNONMCK_118);
GLB_D6_IN9 : PGBUFI
	PORT MAP (Z0 => D6_IN9, A0 => UQNNONMCK_113);
GLB_D6_IN6 : PGBUFI
	PORT MAP (Z0 => D6_IN6, A0 => UQNNONMCK_114);
GLB_D6_X1O : PGXOR2
	PORT MAP (Z0 => D6_X1O, A1 => GND, A0 => D6_G2);
GLB_D6_IN7B : PGINVI
	PORT MAP (ZN0 => D6_IN7B, A0 => UQNNONMCK_115);
GLB_D6_IN1B : PGINVI
	PORT MAP (ZN0 => D6_IN1B, A0 => UQNNONMCK_118);
GLB_D6_IN9B : PGINVI
	PORT MAP (ZN0 => D6_IN9B, A0 => UQNNONMCK_113);
GLB_D6_IN4B : PGINVI
	PORT MAP (ZN0 => D6_IN4B, A0 => UQNNONMCK_119);
GLB_D6_IN0B : PGINVI
	PORT MAP (ZN0 => D6_IN0B, A0 => UQNNONMCK_120);
GLB_D6_IN5B : PGINVI
	PORT MAP (ZN0 => D6_IN5B, A0 => UQNNONMCK_116);
GLB_D6_IN2B : PGINVI
	PORT MAP (ZN0 => D6_IN2B, A0 => UQNNONMCK_121);
GLB_D7_P16 : PGAND2
	PORT MAP (Z0 => D7_P16, A1 => D7_IN15, A0 => D7_IN17);
GLB_D7_P15 : PGAND2
	PORT MAP (Z0 => D7_P15, A1 => D7_IN6, A0 => D7_IN17);
GLB_D7_P14 : PGAND2
	PORT MAP (Z0 => D7_P14, A1 => D7_IN6, A0 => D7_IN15B);
GLB_D7_P12 : PGAND2
	PORT MAP (Z0 => D7_P12, A1 => D7_IN5, A0 => D7_IN17B);
GLB_D7_P11 : PGAND3
	PORT MAP (Z0 => D7_P11, A2 => D7_IN5, A1 => D7_IN11B, A0 => D7_IN16);
GLB_D7_P10 : PGAND3
	PORT MAP (Z0 => D7_P10, A2 => D7_IN8, A1 => D7_IN11, A0 => D7_IN17);
GLB_D7_P9 : PGAND5
	PORT MAP (Z0 => D7_P9, A4 => D7_IN4, A3 => D7_IN5B, A2 => D7_IN11B, 
	A1 => D7_IN16B, A0 => D7_IN17);
GLB_D7_P8 : PGAND5
	PORT MAP (Z0 => D7_P8, A4 => D7_IN0, A3 => D7_IN5B, A2 => D7_IN11B, 
	A1 => D7_IN16B, A0 => D7_IN17);
GLB_D7_P7 : PGAND2
	PORT MAP (Z0 => D7_P7, A1 => D7_IN16, A0 => D7_IN17B);
GLB_D7_P6 : PGAND3
	PORT MAP (Z0 => D7_P6, A2 => D7_IN11B, A1 => D7_IN16B, A0 => D7_IN17);
GLB_D7_P5 : PGAND4
	PORT MAP (Z0 => D7_P5, A3 => D7_IN8, A2 => D7_IN11, A1 => D7_IN14, 
	A0 => D7_IN17);
GLB_D7_P3 : PGAND2
	PORT MAP (Z0 => D7_P3, A1 => D7_IN4, A0 => D7_IN17B);
GLB_D7_P2 : PGAND3
	PORT MAP (Z0 => D7_P2, A2 => D7_IN4, A1 => D7_IN11B, A0 => D7_IN16);
GLB_D7_P1 : PGAND3
	PORT MAP (Z0 => D7_P1, A2 => D7_IN4, A1 => D7_IN5, A0 => D7_IN11B);
GLB_D7_P0 : PGAND6
	PORT MAP (Z0 => D7_P0, A5 => D7_IN0, A4 => D7_IN4B, A3 => D7_IN5B, 
	A2 => D7_IN11B, A1 => D7_IN16B, A0 => D7_IN17);
GLB_D7_G3 : PGBUFI
	PORT MAP (Z0 => D7_G3, A0 => D7_F1);
GLB_D7_G2 : PGBUFI
	PORT MAP (Z0 => D7_G2, A0 => D7_F5);
GLB_D7_G1 : PGBUFI
	PORT MAP (Z0 => D7_G1, A0 => D7_F4);
GLB_D7_G0 : PGBUFI
	PORT MAP (Z0 => D7_G0, A0 => D7_F0);
GLB_D7_F5 : PGORF73
	PORT MAP (Z0 => D7_F5, A2 => D7_P14, A1 => D7_P15, A0 => D7_P16);
GLB_D7_F4 : PGORF75
	PORT MAP (Z0 => D7_F4, A4 => D7_P8, A3 => D7_P9, A2 => D7_P10, 
	A1 => D7_P11, A0 => D7_P12);
GLB_D7_F1 : PGORF73
	PORT MAP (Z0 => D7_F1, A2 => D7_P5, A1 => D7_P6, A0 => D7_P7);
GLB_D7_F0 : PGORF74
	PORT MAP (Z0 => D7_F0, A3 => D7_P0, A2 => D7_P1, A1 => D7_P2, 
	A0 => D7_P3);
GLB_D7_CLK : PGBUFI
	PORT MAP (Z0 => D7_CLK, A0 => CARRY_ck1f);
GLB_EN : PGBUFI
	PORT MAP (Z0 => EN, A0 => D7_X1O);
GLB_D7_IN15 : PGBUFI
	PORT MAP (Z0 => D7_IN15, A0 => CARRY_grpi);
GLB_D7_IN6 : PGBUFI
	PORT MAP (Z0 => D7_IN6, A0 => UQNN_N6_grpi);
GLB_D7_IN14 : PGBUFI
	PORT MAP (Z0 => D7_IN14, A0 => UQNNONMCK_111);
GLB_D7_IN11 : PGBUFI
	PORT MAP (Z0 => D7_IN11, A0 => LOAD_grpi);
GLB_D7_IN8 : PGBUFI
	PORT MAP (Z0 => D7_IN8, A0 => UQNNONMCK_126);
GLB_D7_IN16 : PGBUFI
	PORT MAP (Z0 => D7_IN16, A0 => UQNNONMCK_152);
GLB_D7_IN5 : PGBUFI
	PORT MAP (Z0 => D7_IN5, A0 => UQNNONMCK_118);
GLB_D7_IN4 : PGBUFI
	PORT MAP (Z0 => D7_IN4, A0 => UQNNONMCK_119);
GLB_D7_IN17 : PGBUFI
	PORT MAP (Z0 => D7_IN17, A0 => EN_ffb);
GLB_D7_IN0 : PGBUFI
	PORT MAP (Z0 => D7_IN0, A0 => UQNNONMCK_120);
GLB_D7_X3O : PGXOR2
	PORT MAP (Z0 => D7_X3O, A1 => GND, A0 => D7_G0);
GLB_D7_X2O : PGXOR2
	PORT MAP (Z0 => D7_X2O, A1 => GND, A0 => D7_G1);
GLB_D7_X1O : PGXOR2
	PORT MAP (Z0 => D7_X1O, A1 => GND, A0 => D7_G2);
GLB_D7_X0O : PGXOR2
	PORT MAP (Z0 => D7_X0O, A1 => GND, A0 => D7_G3);
UQBNONMCK_112 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_149, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D7_CLK, 
	D0 => D7_X3O);
UQBNONMCK_113 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_150, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D7_CLK, 
	D0 => D7_X2O);
UQBNONMCK_114 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_151, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D7_CLK, 
	D0 => D7_X0O);
GLB_D7_IN15B : PGINVI
	PORT MAP (ZN0 => D7_IN15B, A0 => CARRY_grpi);
GLB_D7_IN17B : PGINVI
	PORT MAP (ZN0 => D7_IN17B, A0 => EN_ffb);
GLB_D7_IN16B : PGINVI
	PORT MAP (ZN0 => D7_IN16B, A0 => UQNNONMCK_152);
GLB_D7_IN11B : PGINVI
	PORT MAP (ZN0 => D7_IN11B, A0 => LOAD_grpi);
GLB_D7_IN5B : PGINVI
	PORT MAP (ZN0 => D7_IN5B, A0 => UQNNONMCK_118);
GLB_D7_IN4B : PGINVI
	PORT MAP (ZN0 => D7_IN4B, A0 => UQNNONMCK_119);
IOC_L2L_KEYWD_RESET : PXIN
	PORT MAP (Z0 => L2L_KEYWD_RESETb, XI0 => XRESET);
IOC_CLK1X : PXIN
	PORT MAP (Z0 => CLK1X, XI0 => CLK1);
IOC_CLKX : PXIN
	PORT MAP (Z0 => CLKX, XI0 => CLK);
IOC_Y2 : PXOUT
	PORT MAP (XO0 => Y2, A0 => IO43_OBUFI);
IOC_IO43_OBUFI : PGINVI
	PORT MAP (ZN0 => IO43_OBUFI, A0 => AND_1073_iomux);
IOC_Y1 : PXOUT
	PORT MAP (XO0 => Y1, A0 => IO46_OBUFI);
IOC_IO46_OBUFI : PGINVI
	PORT MAP (ZN0 => IO46_OBUFI, A0 => AND_1075_iomux);
UQBNONMCK_115 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_99, A0 => IO16_OBUFI);
IOC_IO16_OBUFI : PGINVI
	PORT MAP (ZN0 => IO16_OBUFI, A0 => AND_1071_buff1_iomux);
UQBNONMCK_116 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_100, A0 => IO17_OBUFI);
IOC_IO17_OBUFI : PGINVI
	PORT MAP (ZN0 => IO17_OBUFI, A0 => AND_1069_buff1_iomux);
UQBNONMCK_117 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_101, A0 => IO18_OBUFI);
IOC_IO18_OBUFI : PGINVI
	PORT MAP (ZN0 => IO18_OBUFI, A0 => AND_1068_buff1_iomux);
UQBNONMCK_118 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_102, A0 => IO19_OBUFI);
IOC_IO19_OBUFI : PGINVI
	PORT MAP (ZN0 => IO19_OBUFI, A0 => AND_1070_buff1_iomux);
UQBNONMCK_119 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_103, A0 => IO48_OBUFI);
IOC_IO48_OBUFI : PGBUFI
	PORT MAP (Z0 => IO48_OBUFI, A0 => N_143_I_iomux);
UQBNONMCK_120 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_104, A0 => IO49_OBUFI);
IOC_IO49_OBUFI : PGBUFI
	PORT MAP (Z0 => IO49_OBUFI, A0 => N_145_I_buff1_iomux);
UQBNONMCK_121 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_105, A0 => IO50_OBUFI);
IOC_IO50_OBUFI : PGBUFI
	PORT MAP (Z0 => IO50_OBUFI, A0 => N_150_I_iomux);
UQBNONMCK_122 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_106, A0 => IO51_OBUFI);
IOC_IO51_OBUFI : PGBUFI
	PORT MAP (Z0 => IO51_OBUFI, A0 => N_148_I_iomux);
UQBNONMCK_123 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_107, A0 => IO52_OBUFI);
IOC_IO52_OBUFI : PGBUFI
	PORT MAP (Z0 => IO52_OBUFI, A0 => N_155_I_buff1_iomux);
UQBNONMCK_124 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_108, A0 => IO53_OBUFI);
IOC_IO53_OBUFI : PGBUFI
	PORT MAP (Z0 => IO53_OBUFI, A0 => OR_759_iomux);
UQBNONMCK_125 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_109, A0 => IO54_OBUFI);
IOC_IO54_OBUFI : PGBUFI
	PORT MAP (Z0 => IO54_OBUFI, A0 => OR_763_iomux);
UQBNONMCK_126 : PXOUT
	PORT MAP (XO0 => UQNNONMCK_110, A0 => IO55_OBUFI);
IOC_IO55_OBUFI : PGBUFI
	PORT MAP (Z0 => IO55_OBUFI, A0 => VCC_1283_buff1_iomux);
IOC_R2 : PXOUT
	PORT MAP (XO0 => R2, A0 => IO44_OBUFI);
IOC_IO44_OBUFI : PGINVI
	PORT MAP (ZN0 => IO44_OBUFI, A0 => DEF_1233_iomux);
IOC_R1 : PXOUT
	PORT MAP (XO0 => R1, A0 => IO47_OBUFI);
IOC_IO47_OBUFI : PGBUFI
	PORT MAP (Z0 => IO47_OBUFI, A0 => UQNNONMCK_127);
IOC_G2 : PXOUT
	PORT MAP (XO0 => G2, A0 => IO42_OBUFI);
IOC_IO42_OBUFI : PGINVI
	PORT MAP (ZN0 => IO42_OBUFI, A0 => AND_1074_iomux);
IOC_G1 : PXOUT
	PORT MAP (XO0 => G1, A0 => IO45_OBUFI);
IOC_IO45_OBUFI : PGINVI
	PORT MAP (ZN0 => IO45_OBUFI, A0 => AND_1072_iomux);
UQBNONMCK_127 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_111, A0 => UQNNONMCK_128);
UQBNONMCK_128 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_112, A0 => UQNNONMCK_137);
UQBNONMCK_129 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_138, A0 => UQNNONMCK_137);
UQBNONMCK_130 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_127, A0 => UQNNONMCK_137);
GRP_VCC_1283_grpi : PGBUFI
	PORT MAP (Z0 => VCC_1283_grpi, A0 => VCC_1283);
GRP_N_155_I_grpi : PGBUFI
	PORT MAP (Z0 => N_155_I_grpi, A0 => N_155_I);
GRP_N_145_I_grpi : PGBUFI
	PORT MAP (Z0 => N_145_I_grpi, A0 => N_145_I);
UQBNONMCK_131 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_130, A0 => UQNNONMCK_129);
UQBNONMCK_132 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_113, A0 => UQNNONMCK_129);
UQBNONMCK_133 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_145, A0 => UQNNONMCK_143);
UQBNONMCK_134 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_114, A0 => UQNNONMCK_143);
UQBNONMCK_135 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_146, A0 => UQNNONMCK_144);
UQBNONMCK_136 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_115, A0 => UQNNONMCK_144);
UQBNONMCK_137 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_116, A0 => UQNNONMCK_142);
UQBNONMCK_138 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_117, A0 => UQNNONMCK_151);
UQBNONMCK_139 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_152, A0 => UQNNONMCK_151);
UQBNONMCK_140 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_118, A0 => UQNNONMCK_150);
UQBNONMCK_141 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_119, A0 => UQNNONMCK_149);
UQBNONMCK_142 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_120, A0 => UQNNONMCK_141);
UQBNONMCK_143 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_136, A0 => UQNNONMCK_134);
UQBNONMCK_144 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_121, A0 => UQNNONMCK_134);
GRP_LOAD_grpi : PGBUFI
	PORT MAP (Z0 => LOAD_grpi, A0 => LOAD);
GRP_CARRY_grpi : PGBUFI
	PORT MAP (Z0 => CARRY_grpi, A0 => CARRY);
GRP_CARRY_ck1f : PGBUFI
	PORT MAP (Z0 => CARRY_ck1f, A0 => CARRY);
UQBNONMCK_145 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_122, A0 => UQNNONMCK_132);
UQBNONMCK_146 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_133, A0 => UQNNONMCK_131);
UQBNONMCK_147 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_123, A0 => UQNNONMCK_131);
UQBNONMCK_148 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_124, A0 => UQNNONMCK_147);
UQBNONMCK_149 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_148, A0 => UQNNONMCK_147);
GRP_CLKX_clk0 : PXIN
	PORT MAP (Z0 => CLKX_clk0, XI0 => CLKX);
GRP_AND_1071_grpi : PGBUFI
	PORT MAP (Z0 => AND_1071_grpi, A0 => AND_1071);
GRP_AND_1070_grpi : PGBUFI
	PORT MAP (Z0 => AND_1070_grpi, A0 => AND_1070);
GRP_AND_1069_grpi : PGBUFI
	PORT MAP (Z0 => AND_1069_grpi, A0 => AND_1069);
GRP_AND_1068_grpi : PGBUFI
	PORT MAP (Z0 => AND_1068_grpi, A0 => AND_1068);
UQBNONMCK_150 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_125, A0 => UQNNONMCK_135);
GRP_AND_1071_buff1_iomux : PGBUFI
	PORT MAP (Z0 => AND_1071_buff1_iomux, A0 => AND_1071_buff1);
GRP_AND_1069_buff1_iomux : PGBUFI
	PORT MAP (Z0 => AND_1069_buff1_iomux, A0 => AND_1069_buff1);
GRP_AND_1068_buff1_iomux : PGBUFI
	PORT MAP (Z0 => AND_1068_buff1_iomux, A0 => AND_1068_buff1);
GRP_AND_1070_buff1_iomux : PGBUFI
	PORT MAP (Z0 => AND_1070_buff1_iomux, A0 => AND_1070_buff1);
GRP_CLK1X_clk2 : PXIN
	PORT MAP (Z0 => CLK1X_clk2, XI0 => CLK1X);
GRP_AND_1074_iomux : PGBUFI
	PORT MAP (Z0 => AND_1074_iomux, A0 => AND_1074);
GRP_AND_1073_iomux : PGBUFI
	PORT MAP (Z0 => AND_1073_iomux, A0 => AND_1073);
GRP_AND_1072_iomux : PGBUFI
	PORT MAP (Z0 => AND_1072_iomux, A0 => AND_1072);
UQBNONMCK_151 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_140, A0 => UQNNONMCK_139);
UQBNONMCK_152 : PGBUFI
	PORT MAP (Z0 => UQNNONMCK_126, A0 => UQNNONMCK_139);
GRP_UQNN_N6_grpi : PGBUFI
	PORT MAP (Z0 => UQNN_N6_grpi, A0 => UQNN_N6);
GRP_DEF_1233_iomux : PGBUFI
	PORT MAP (Z0 => DEF_1233_iomux, A0 => DEF_1233);
GRP_AND_1075_iomux : PGBUFI
	PORT MAP (Z0 => AND_1075_iomux, A0 => AND_1075);
GRP_N_155_I_buff1_iomux : PGBUFI
	PORT MAP (Z0 => N_155_I_buff1_iomux, A0 => N_155_I_buff1);
GRP_N_145_I_buff1_iomux : PGBUFI
	PORT MAP (Z0 => N_145_I_buff1_iomux, A0 => N_145_I_buff1);
GRP_VCC_1283_buff1_iomux : PGBUFI
	PORT MAP (Z0 => VCC_1283_buff1_iomux, A0 => VCC_1283_buff1);
GRP_OR_763_iomux : PGBUFI
	PORT MAP (Z0 => OR_763_iomux, A0 => OR_763);
GRP_EN_grpi : PGBUFI
	PORT MAP (Z0 => EN_grpi, A0 => EN);
GRP_EN_ffb : PGBUFI
	PORT MAP (Z0 => EN_ffb, A0 => EN);
GRP_N_150_I_iomux : PGBUFI
	PORT MAP (Z0 => N_150_I_iomux, A0 => N_150_I);
GRP_N_148_I_iomux : PGBUFI
	PORT MAP (Z0 => N_148_I_iomux, A0 => N_148_I);
GRP_N_143_I_iomux : PGBUFI
	PORT MAP (Z0 => N_143_I_iomux, A0 => N_143_I);
GRP_OR_759_iomux : PGBUFI
	PORT MAP (Z0 => OR_759_iomux, A0 => OR_759);
GRP_L2L_KEYWD_RESET_glb : PXIN
	PORT MAP (Z0 => L2L_KEYWD_RESET_glbb, XI0 => L2L_KEYWD_RESETb);
END trafic_STRUCTURE;