trafic.vto

CPLD lattice1032 VHDL实现交通灯控制！

UQBNONMCK_105 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_137, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => C3_CLK, 
	D0 => C3_X3O);
GLB_DEF_1233 : PGDFFR
	PORT MAP (Q0 => DEF_1233, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => C3_CLK, 
	D0 => C3_X0O);
GLB_C3_CLK : PGINVI
	PORT MAP (ZN0 => C3_CLK, A0 => CARRY_ck1f);
GLB_C3_IN9B : PGINVI
	PORT MAP (ZN0 => C3_IN9B, A0 => UQNNONMCK_113);
GLB_C3_IN8B : PGINVI
	PORT MAP (ZN0 => C3_IN8B, A0 => UQNNONMCK_126);
GLB_C3_IN7B : PGINVI
	PORT MAP (ZN0 => C3_IN7B, A0 => UQNNONMCK_115);
GLB_C3_IN6B : PGINVI
	PORT MAP (ZN0 => C3_IN6B, A0 => UQNNONMCK_114);
GLB_C3_IN5B : PGINVI
	PORT MAP (ZN0 => C3_IN5B, A0 => UQNNONMCK_116);
GLB_C3_IN4B : PGINVI
	PORT MAP (ZN0 => C3_IN4B, A0 => UQNNONMCK_119);
GLB_C3_IN3B : PGINVI
	PORT MAP (ZN0 => C3_IN3B, A0 => UQNNONMCK_117);
GLB_C3_IN1B : PGINVI
	PORT MAP (ZN0 => C3_IN1B, A0 => UQNNONMCK_118);
GLB_C3_IN0B : PGINVI
	PORT MAP (ZN0 => C3_IN0B, A0 => UQNNONMCK_120);
GLB_D0_P13 : PGBUFI
	PORT MAP (Z0 => D0_P13, A0 => D0_IN11);
GLB_D0_P8 : PGBUFI
	PORT MAP (Z0 => D0_P8, A0 => D0_IN10);
GLB_D0_P0 : PGBUFI
	PORT MAP (Z0 => D0_P0, A0 => D0_IN8);
GLB_D0_G3 : PGBUFI
	PORT MAP (Z0 => D0_G3, A0 => GND);
GLB_D0_G2 : PGBUFI
	PORT MAP (Z0 => D0_G2, A0 => GND);
GLB_D0_G0 : PGBUFI
	PORT MAP (Z0 => D0_G0, A0 => GND);
GLB_D0_P0_xa : PGBUFI
	PORT MAP (Z0 => D0_P0_xa, A0 => D0_P0);
GLB_VCC_1283_buff1 : PGBUFI
	PORT MAP (Z0 => VCC_1283_buff1, A0 => D0_X3O);
GLB_D0_P8_xa : PGBUFI
	PORT MAP (Z0 => D0_P8_xa, A0 => D0_P8);
GLB_N_145_I_buff1 : PGBUFI
	PORT MAP (Z0 => N_145_I_buff1, A0 => D0_X1O);
GLB_D0_P13_xa : PGBUFI
	PORT MAP (Z0 => D0_P13_xa, A0 => D0_P13);
GLB_N_155_I_buff1 : PGBUFI
	PORT MAP (Z0 => N_155_I_buff1, A0 => D0_X0O);
GLB_D0_IN11 : PGBUFI
	PORT MAP (Z0 => D0_IN11, A0 => N_155_I_grpi);
GLB_D0_IN10 : PGBUFI
	PORT MAP (Z0 => D0_IN10, A0 => N_145_I_grpi);
GLB_D0_IN8 : PGBUFI
	PORT MAP (Z0 => D0_IN8, A0 => VCC_1283_grpi);
GLB_D0_X3O : PGXOR2
	PORT MAP (Z0 => D0_X3O, A1 => D0_P0_xa, A0 => D0_G0);
GLB_D0_X1O : PGXOR2
	PORT MAP (Z0 => D0_X1O, A1 => D0_P8_xa, A0 => D0_G2);
GLB_D0_X0O : PGXOR2
	PORT MAP (Z0 => D0_X0O, A1 => D0_P13_xa, A0 => D0_G3);
GLB_D1_P19 : PGAND5
	PORT MAP (Z0 => D1_P19, A4 => D1_IN2B, A3 => D1_IN5B, A2 => D1_IN6, 
	A1 => D1_IN7, A0 => D1_IN9);
GLB_D1_P18 : PGAND5
	PORT MAP (Z0 => D1_P18, A4 => D1_IN2B, A3 => D1_IN5, A2 => D1_IN6B, 
	A1 => D1_IN7, A0 => D1_IN9B);
GLB_D1_P17 : PGAND5
	PORT MAP (Z0 => D1_P17, A4 => D1_IN0B, A3 => D1_IN1, A2 => D1_IN2, 
	A1 => D1_IN3, A0 => D1_IN4);
GLB_D1_P16 : PGAND4
	PORT MAP (Z0 => D1_P16, A3 => D1_IN0B, A2 => D1_IN1B, A1 => D1_IN2, 
	A0 => D1_IN4B);
GLB_D1_P15 : PGAND4
	PORT MAP (Z0 => D1_P15, A3 => D1_IN2B, A2 => D1_IN5B, A1 => D1_IN7B, 
	A0 => D1_IN9B);
GLB_D1_P14 : PGAND5
	PORT MAP (Z0 => D1_P14, A4 => D1_IN0, A3 => D1_IN1B, A2 => D1_IN2, 
	A1 => D1_IN3B, A0 => D1_IN4);
GLB_D1_P13 : PGAND8
	PORT MAP (Z0 => D1_P13, A7 => D1_IN0B, A6 => D1_IN1B, A5 => D1_IN3B, 
	A4 => D1_IN4B, A3 => D1_IN5B, A2 => D1_IN6B, A1 => D1_IN7B, 
	A0 => D1_IN9B);
GLB_D1_P3 : PGBUFI
	PORT MAP (Z0 => D1_P3, A0 => D1_IN17);
GLB_D1_P0 : PGAND8
	PORT MAP (Z0 => D1_P0, A7 => D1_IN0B, A6 => D1_IN1B, A5 => D1_IN3B, 
	A4 => D1_IN4B, A3 => D1_IN5B, A2 => D1_IN6B, A1 => D1_IN7B, 
	A0 => D1_IN9B);
GLB_D1_G3 : PGBUFI
	PORT MAP (Z0 => D1_G3, A0 => GND);
GLB_D1_G1 : PGBUFI
	PORT MAP (Z0 => D1_G1, A0 => D1_F5);
GLB_D1_G0 : PGBUFI
	PORT MAP (Z0 => D1_G0, A0 => D1_F0);
GLB_D1_F5 : PGORF76
	PORT MAP (Z0 => D1_F5, A5 => D1_P14, A4 => D1_P15, A3 => D1_P16, 
	A2 => D1_P19, A1 => D1_P17, A0 => D1_P18);
GLB_D1_F0 : PGBUFI
	PORT MAP (Z0 => D1_F0, A0 => D1_P3);
GLB_D1_P0_xa : PGBUFI
	PORT MAP (Z0 => D1_P0_xa, A0 => D1_P0);
GLB_OR_763 : PGBUFI
	PORT MAP (Z0 => OR_763, A0 => D1_X2O);
GLB_D1_P13_xa : PGBUFI
	PORT MAP (Z0 => D1_P13_xa, A0 => D1_P13);
GLB_D1_IN9 : PGBUFI
	PORT MAP (Z0 => D1_IN9, A0 => UQNNONMCK_113);
GLB_D1_IN6 : PGBUFI
	PORT MAP (Z0 => D1_IN6, A0 => UQNNONMCK_114);
GLB_D1_IN7 : PGBUFI
	PORT MAP (Z0 => D1_IN7, A0 => UQNNONMCK_115);
GLB_D1_IN5 : PGBUFI
	PORT MAP (Z0 => D1_IN5, A0 => UQNNONMCK_116);
GLB_D1_IN3 : PGBUFI
	PORT MAP (Z0 => D1_IN3, A0 => UQNNONMCK_117);
GLB_D1_IN1 : PGBUFI
	PORT MAP (Z0 => D1_IN1, A0 => UQNNONMCK_118);
GLB_D1_IN4 : PGBUFI
	PORT MAP (Z0 => D1_IN4, A0 => UQNNONMCK_119);
GLB_D1_IN2 : PGBUFI
	PORT MAP (Z0 => D1_IN2, A0 => UQNNONMCK_121);
GLB_D1_IN0 : PGBUFI
	PORT MAP (Z0 => D1_IN0, A0 => UQNNONMCK_120);
GLB_D1_IN17 : PGBUFI
	PORT MAP (Z0 => D1_IN17, A0 => UQNNONMCK_140);
GLB_D1_X3O : PGXOR2
	PORT MAP (Z0 => D1_X3O, A1 => D1_P0_xa, A0 => D1_G0);
GLB_D1_X2O : PGXOR2
	PORT MAP (Z0 => D1_X2O, A1 => GND, A0 => D1_G1);
GLB_D1_X0O : PGXOR2
	PORT MAP (Z0 => D1_X0O, A1 => D1_P13_xa, A0 => D1_G3);
UQBNONMCK_106 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_139, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D1_CLK, 
	D0 => D1_X3O);
GLB_LOAD : PGDFFR
	PORT MAP (Q0 => LOAD, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D1_CLK, 
	D0 => D1_X0O);
GLB_D1_CLK : PGINVI
	PORT MAP (ZN0 => D1_CLK, A0 => CARRY_ck1f);
GLB_D1_IN2B : PGINVI
	PORT MAP (ZN0 => D1_IN2B, A0 => UQNNONMCK_121);
GLB_D1_IN9B : PGINVI
	PORT MAP (ZN0 => D1_IN9B, A0 => UQNNONMCK_113);
GLB_D1_IN7B : PGINVI
	PORT MAP (ZN0 => D1_IN7B, A0 => UQNNONMCK_115);
GLB_D1_IN6B : PGINVI
	PORT MAP (ZN0 => D1_IN6B, A0 => UQNNONMCK_114);
GLB_D1_IN5B : PGINVI
	PORT MAP (ZN0 => D1_IN5B, A0 => UQNNONMCK_116);
GLB_D1_IN4B : PGINVI
	PORT MAP (ZN0 => D1_IN4B, A0 => UQNNONMCK_119);
GLB_D1_IN3B : PGINVI
	PORT MAP (ZN0 => D1_IN3B, A0 => UQNNONMCK_117);
GLB_D1_IN1B : PGINVI
	PORT MAP (ZN0 => D1_IN1B, A0 => UQNNONMCK_118);
GLB_D1_IN0B : PGINVI
	PORT MAP (ZN0 => D1_IN0B, A0 => UQNNONMCK_120);
GLB_D3_P16 : PGAND2
	PORT MAP (Z0 => D3_P16, A1 => D3_IN8B, A0 => D3_IN11);
GLB_D3_P15 : PGAND3
	PORT MAP (Z0 => D3_P15, A2 => D3_IN11B, A1 => D3_IN16, A0 => D3_IN17);
GLB_D3_P14 : PGAND3
	PORT MAP (Z0 => D3_P14, A2 => D3_IN9, A1 => D3_IN11B, A0 => D3_IN16);
GLB_D3_P13 : PGAND5
	PORT MAP (Z0 => D3_P13, A4 => D3_IN5, A3 => D3_IN9B, A2 => D3_IN11B, 
	A1 => D3_IN16B, A0 => D3_IN17B);
GLB_D3_P12 : PGAND6
	PORT MAP (Z0 => D3_P12, A5 => D3_IN0B, A4 => D3_IN1B, A3 => D3_IN4B, 
	A2 => D3_IN6, A1 => D3_IN7B, A0 => D3_IN11B);
GLB_D3_P8 : PGAND2
	PORT MAP (Z0 => D3_P8, A1 => D3_IN11B, A0 => D3_IN17B);
GLB_D3_P7 : PGAND3
	PORT MAP (Z0 => D3_P7, A2 => D3_IN5, A1 => D3_IN11B, A0 => D3_IN17);
GLB_D3_P6 : PGAND3
	PORT MAP (Z0 => D3_P6, A2 => D3_IN5, A1 => D3_IN9, A0 => D3_IN11B);
GLB_D3_P5 : PGAND3
	PORT MAP (Z0 => D3_P5, A2 => D3_IN5, A1 => D3_IN11B, A0 => D3_IN16);
GLB_D3_P4 : PGAND5
	PORT MAP (Z0 => D3_P4, A4 => D3_IN5B, A3 => D3_IN9B, A2 => D3_IN11B, 
	A1 => D3_IN16B, A0 => D3_IN17B);
GLB_D3_P3 : PGAND2
	PORT MAP (Z0 => D3_P3, A1 => D3_IN0, A0 => D3_IN6B);
GLB_D3_P2 : PGAND3
	PORT MAP (Z0 => D3_P2, A2 => D3_IN0, A1 => D3_IN7, A0 => D3_IN11B);
GLB_D3_P1 : PGAND3
	PORT MAP (Z0 => D3_P1, A2 => D3_IN0, A1 => D3_IN1, A0 => D3_IN11B);
GLB_D3_P0 : PGAND3
	PORT MAP (Z0 => D3_P0, A2 => D3_IN0, A1 => D3_IN4, A0 => D3_IN11B);
GLB_D3_G2 : PGBUFI
	PORT MAP (Z0 => D3_G2, A0 => GND);
GLB_D3_G0 : PGORF72
	PORT MAP (Z0 => D3_G0, A1 => D3_F0, A0 => D3_F4);
GLB_D3_F4 : PGBUFI
	PORT MAP (Z0 => D3_F4, A0 => D3_P12);
GLB_D3_F3 : PGORF74
	PORT MAP (Z0 => D3_F3, A3 => D3_P13, A2 => D3_P14, A1 => D3_P15, 
	A0 => D3_P16);
GLB_D3_F1 : PGORF74
	PORT MAP (Z0 => D3_F1, A3 => D3_P4, A2 => D3_P5, A1 => D3_P6, 
	A0 => D3_P7);
GLB_D3_F0 : PGORF74
	PORT MAP (Z0 => D3_F0, A3 => D3_P0, A2 => D3_P1, A1 => D3_P2, 
	A0 => D3_P3);
GLB_D3_CLK : PGBUFI
	PORT MAP (Z0 => D3_CLK, A0 => CARRY_ck1f);
GLB_D3_P8_xa : PGBUFI
	PORT MAP (Z0 => D3_P8_xa, A0 => D3_P8);
GLB_D3_IN11 : PGBUFI
	PORT MAP (Z0 => D3_IN11, A0 => LOAD_grpi);
GLB_D3_IN6 : PGBUFI
	PORT MAP (Z0 => D3_IN6, A0 => EN_grpi);
GLB_D3_IN17 : PGBUFI
	PORT MAP (Z0 => D3_IN17, A0 => UQNNONMCK_145);
GLB_D3_IN9 : PGBUFI
	PORT MAP (Z0 => D3_IN9, A0 => UQNNONMCK_113);
GLB_D3_IN16 : PGBUFI
	PORT MAP (Z0 => D3_IN16, A0 => UQNNONMCK_146);
GLB_D3_IN5 : PGBUFI
	PORT MAP (Z0 => D3_IN5, A0 => UQNNONMCK_116);
GLB_D3_IN7 : PGBUFI
	PORT MAP (Z0 => D3_IN7, A0 => UQNNONMCK_117);
GLB_D3_IN1 : PGBUFI
	PORT MAP (Z0 => D3_IN1, A0 => UQNNONMCK_118);
GLB_D3_IN4 : PGBUFI
	PORT MAP (Z0 => D3_IN4, A0 => UQNNONMCK_119);
GLB_D3_IN0 : PGBUFI
	PORT MAP (Z0 => D3_IN0, A0 => UQNNONMCK_120);
GLB_D3_X3O : PGXOR2
	PORT MAP (Z0 => D3_X3O, A1 => GND, A0 => D3_G0);
GLB_D3_X1O : PGXOR2
	PORT MAP (Z0 => D3_X1O, A1 => D3_P8_xa, A0 => D3_G2);
UQBNONMCK_107 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_141, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D3_CLK, 
	D0 => D3_X3O);
UQBNONMCK_108 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_142, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D3_CLK, 
	D0 => D3_F1);
UQBNONMCK_109 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_143, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D3_CLK, 
	D0 => D3_X1O);
UQBNONMCK_110 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_144, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D3_CLK, 
	D0 => D3_F3);
GLB_D3_IN8B : PGINVI
	PORT MAP (ZN0 => D3_IN8B, A0 => UQNNONMCK_126);
GLB_D3_IN7B : PGINVI
	PORT MAP (ZN0 => D3_IN7B, A0 => UQNNONMCK_117);
GLB_D3_IN4B : PGINVI
	PORT MAP (ZN0 => D3_IN4B, A0 => UQNNONMCK_119);
GLB_D3_IN1B : PGINVI
	PORT MAP (ZN0 => D3_IN1B, A0 => UQNNONMCK_118);
GLB_D3_IN0B : PGINVI
	PORT MAP (ZN0 => D3_IN0B, A0 => UQNNONMCK_120);
GLB_D3_IN17B : PGINVI
	PORT MAP (ZN0 => D3_IN17B, A0 => UQNNONMCK_145);
GLB_D3_IN16B : PGINVI
	PORT MAP (ZN0 => D3_IN16B, A0 => UQNNONMCK_146);
GLB_D3_IN9B : PGINVI
	PORT MAP (ZN0 => D3_IN9B, A0 => UQNNONMCK_113);
GLB_D3_IN5B : PGINVI
	PORT MAP (ZN0 => D3_IN5B, A0 => UQNNONMCK_116);
GLB_D3_IN6B : PGINVI
	PORT MAP (ZN0 => D3_IN6B, A0 => EN_grpi);
GLB_D3_IN11B : PGINVI
	PORT MAP (ZN0 => D3_IN11B, A0 => LOAD_grpi);
GLB_D5_P18 : PGAND5
	PORT MAP (Z0 => D5_P18, A4 => D5_IN0B, A3 => D5_IN1, A2 => D5_IN2, 
	A1 => D5_IN3B, A0 => D5_IN4B);
GLB_D5_P17 : PGAND5
	PORT MAP (Z0 => D5_P17, A4 => D5_IN2B, A3 => D5_IN5B, A2 => D5_IN6B, 
	A1 => D5_IN7B, A0 => D5_IN9);
GLB_D5_P16 : PGAND4
	PORT MAP (Z0 => D5_P16, A3 => D5_IN0, A2 => D5_IN1, A1 => D5_IN2, 
	A0 => D5_IN4);
GLB_D5_P15 : PGAND4
	PORT MAP (Z0 => D5_P15, A3 => D5_IN2B, A2 => D5_IN5, A1 => D5_IN7, 
	A0 => D5_IN9);
GLB_D5_P14 : PGAND4
	PORT MAP (Z0 => D5_P14, A3 => D5_IN2B, A2 => D5_IN5, A1 => D5_IN6B, 
	A0 => D5_IN7);
GLB_D5_P13 : PGAND4
	PORT MAP (Z0 => D5_P13, A3 => D5_IN0, A2 => D5_IN2, A1 => D5_IN3B, 
	A0 => D5_IN4);
GLB_D5_P12 : PGAND5
	PORT MAP (Z0 => D5_P12, A4 => D5_IN0B, A3 => D5_IN1B, A2 => D5_IN2, 
	A1 => D5_IN3B, A0 => D5_IN4);
GLB_D5_P11 : PGAND5
	PORT MAP (Z0 => D5_P11, A4 => D5_IN0B, A3 => D5_IN1B, A2 => D5_IN2, 
	A1 => D5_IN3, A0 => D5_IN4B);
GLB_D5_P10 : PGAND5
	PORT MAP (Z0 => D5_P10, A4 => D5_IN2B, A3 => D5_IN5B, A2 => D5_IN6B, 
	A1 => D5_IN7, A0 => D5_IN9B);
GLB_D5_P9 : PGAND5
	PORT MAP (Z0 => D5_P9, A4 => D5_IN2B, A3 => D5_IN5B, A2 => D5_IN6, 
	A1 => D5_IN7B, A0 => D5_IN9B);
GLB_D5_P8 : PGBUFI
	PORT MAP (Z0 => D5_P8, A0 => D5_IN16B);
GLB_D5_P7 : PGAND4
	PORT MAP (Z0 => D5_P7, A3 => D5_IN1, A2 => D5_IN2, A1 => D5_IN3, 
	A0 => D5_IN4);
GLB_D5_P6 : PGAND4
	PORT MAP (Z0 => D5_P6, A3 => D5_IN2B, A2 => D5_IN6, A1 => D5_IN7, 
	A0 => D5_IN9);
GLB_D5_P5 : PGAND5
	PORT MAP (Z0 => D5_P5, A4 => D5_IN0, A3 => D5_IN1, A2 => D5_IN2, 
	A1 => D5_IN3B, A0 => D5_IN4B);
GLB_D5_P4 : PGAND5
	PORT MAP (Z0 => D5_P4, A4 => D5_IN2B, A3 => D5_IN5, A2 => D5_IN6B, 
	A1 => D5_IN7B, A0 => D5_IN9);
GLB_D5_P3 : PGAND5
	PORT MAP (Z0 => D5_P3, A4 => D5_IN0, A3 => D5_IN1B, A2 => D5_IN2, 
	A1 => D5_IN3, A0 => D5_IN4);
GLB_D5_P2 : PGAND5
	PORT MAP (Z0 => D5_P2, A4 => D5_IN0, A3 => D5_IN1, A2 => D5_IN2, 
	A1 => D5_IN3, A0 => D5_IN4B);
GLB_D5_P1 : PGAND5
	PORT MAP (Z0 => D5_P1, A4 => D5_IN2B, A3 => D5_IN5, A2 => D5_IN6, 
	A1 => D5_IN7, A0 => D5_IN9B);
GLB_D5_P0 : PGAND5
	PORT MAP (Z0 => D5_P0, A4 => D5_IN2B, A3 => D5_IN5, A2 => D5_IN6, 
	A1 => D5_IN7B, A0 => D5_IN9);
GLB_D5_G3 : PGORF72
	PORT MAP (Z0 => D5_G3, A1 => D5_F0, A0 => D5_F4);
GLB_D5_G2 : PGBUFI
	PORT MAP (Z0 => D5_G2, A0 => GND);
GLB_D5_G1 : PGBUFI
	PORT MAP (Z0 => D5_G1, A0 => D5_F5);
GLB_D5_G0 : PGORF72
	PORT MAP (Z0 => D5_G0, A1 => D5_F1, A0 => D5_F4);
GLB_D5_F5 : PGORF76
	PORT MAP (Z0 => D5_F5, A5 => D5_P13, A4 => D5_P14, A3 => D5_P15, 
	A2 => D5_P16, A1 => D5_P17, A0 => D5_P18);
GLB_D5_F4 : PGORF74
	PORT MAP (Z0 => D5_F4, A3 => D5_P9, A2 => D5_P10, A1 => D5_P11, 
	A0 => D5_P12);
GLB_D5_F1 : PGORF74
	PORT MAP (Z0 => D5_F1, A3 => D5_P4, A2 => D5_P5, A1 => D5_P6, 
	A0 => D5_P7);
GLB_D5_F0 : PGORF74
	PORT MAP (Z0 => D5_F0, A3 => D5_P0, A2 => D5_P1, A1 => D5_P2, 
	A0 => D5_P3);
GLB_D5_CLK : PGBUFI
	PORT MAP (Z0 => D5_CLK, A0 => CLKX_clk0);
GLB_N_148_I : PGBUFI
	PORT MAP (Z0 => N_148_I, A0 => D5_X3O);
GLB_N_150_I : PGBUFI
	PORT MAP (Z0 => N_150_I, A0 => D5_X2O);
GLB_D5_P8_xa : PGBUFI
	PORT MAP (Z0 => D5_P8_xa, A0 => D5_P8);
GLB_N_143_I : PGBUFI
	PORT MAP (Z0 => N_143_I, A0 => D5_X0O);
GLB_D5_IN4 : PGBUFI
	PORT MAP (Z0 => D5_IN4, A0 => UQNNONMCK_119);
GLB_D5_IN3 : PGBUFI
	PORT MAP (Z0 => D5_IN3, A0 => UQNNONMCK_117);
GLB_D5_IN2 : PGBUFI
	PORT MAP (Z0 => D5_IN2, A0 => UQNNONMCK_121);
GLB_D5_IN1 : PGBUFI
	PORT MAP (Z0 => D5_IN1, A0 => UQNNONMCK_118);
GLB_D5_IN0 : PGBUFI
	PORT MAP (Z0 => D5_IN0, A0 => UQNNONMCK_120);
GLB_D5_IN7 : PGBUFI
	PORT MAP (Z0 => D5_IN7, A0 => UQNNONMCK_115);
GLB_D5_IN9 : PGBUFI
	PORT MAP (Z0 => D5_IN9, A0 => UQNNONMCK_113);
GLB_D5_IN6 : PGBUFI
	PORT MAP (Z0 => D5_IN6, A0 => UQNNONMCK_114);
GLB_D5_IN5 : PGBUFI
	PORT MAP (Z0 => D5_IN5, A0 => UQNNONMCK_116);
GLB_D5_X3O : PGXOR2
	PORT MAP (Z0 => D5_X3O, A1 => GND, A0 => D5_G0);
GLB_D5_X2O : PGXOR2
	PORT MAP (Z0 => D5_X2O, A1 => GND, A0 => D5_G1);
GLB_D5_X1O : PGXOR2
	PORT MAP (Z0 => D5_X1O, A1 => D5_P8_xa, A0 => D5_G2);
GLB_D5_X0O : PGXOR2
	PORT MAP (Z0 => D5_X0O, A1 => GND, A0 => D5_G3);
UQBNONMCK_111 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_147, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => D5_CLK, 
	D0 => D5_X1O);
GLB_D5_IN0B : PGINVI
	PORT MAP (ZN0 => D5_IN0B, A0 => UQNNONMCK_120);
GLB_D5_IN5B : PGINVI
	PORT MAP (ZN0 => D5_IN5B, A0 => UQNNONMCK_116);
GLB_D5_IN16B : PGINVI
	PORT MAP (ZN0 => D5_IN16B, A0 => UQNNONMCK_148);