trafic.vto

CPLD lattice1032 VHDL实现交通灯控制！

	PORT MAP (Z0 => UQNNONMCK_128, A0 => A0_X1O);
GLB_A0_IN15 : PGBUFI
	PORT MAP (Z0 => A0_IN15, A0 => UQNNONMCK_112);
GLB_A0_X1O : PGXOR2
	PORT MAP (Z0 => A0_X1O, A1 => A0_P8_xa, A0 => A0_G2);
GLB_A1_P18 : PGAND4
	PORT MAP (Z0 => A1_P18, A3 => A1_IN11, A2 => A1_IN13, A1 => A1_IN14B, 
	A0 => A1_IN15B);
GLB_A1_P17 : PGAND4
	PORT MAP (Z0 => A1_P17, A3 => A1_IN11B, A2 => A1_IN12, A1 => A1_IN13, 
	A0 => A1_IN14B);
GLB_A1_P16 : PGAND3
	PORT MAP (Z0 => A1_P16, A2 => A1_IN9, A1 => A1_IN10B, A0 => A1_IN13B);
GLB_A1_P15 : PGAND3
	PORT MAP (Z0 => A1_P15, A2 => A1_IN12, A1 => A1_IN13, A0 => A1_IN15B);
GLB_A1_P14 : PGAND4
	PORT MAP (Z0 => A1_P14, A3 => A1_IN8B, A2 => A1_IN9, A1 => A1_IN13B, 
	A0 => A1_IN16B);
GLB_A1_P13 : PGAND4
	PORT MAP (Z0 => A1_P13, A3 => A1_IN8, A2 => A1_IN10B, A1 => A1_IN13B, 
	A0 => A1_IN16B);
GLB_A1_P12 : PGAND3
	PORT MAP (Z0 => A1_P12, A2 => A1_IN11, A1 => A1_IN12B, A0 => A1_IN13);
GLB_A1_P11 : PGAND4
	PORT MAP (Z0 => A1_P11, A3 => A1_IN8, A2 => A1_IN10B, A1 => A1_IN13B, 
	A0 => A1_IN16B);
GLB_A1_P7 : PGAND3
	PORT MAP (Z0 => A1_P7, A2 => A1_IN4B, A1 => A1_IN9, A0 => A1_IN16);
GLB_A1_P6 : PGAND4
	PORT MAP (Z0 => A1_P6, A3 => A1_IN4B, A2 => A1_IN8, A1 => A1_IN9B, 
	A0 => A1_IN16B);
GLB_A1_P5 : PGAND4
	PORT MAP (Z0 => A1_P5, A3 => A1_IN4B, A2 => A1_IN9B, A1 => A1_IN10, 
	A0 => A1_IN16B);
GLB_A1_P3 : PGAND3
	PORT MAP (Z0 => A1_P3, A2 => A1_IN8, A1 => A1_IN9B, A0 => A1_IN13B);
GLB_A1_P2 : PGAND4
	PORT MAP (Z0 => A1_P2, A3 => A1_IN12, A2 => A1_IN13, A1 => A1_IN14, 
	A0 => A1_IN15);
GLB_A1_P1 : PGAND4
	PORT MAP (Z0 => A1_P1, A3 => A1_IN11, A2 => A1_IN13, A1 => A1_IN14B, 
	A0 => A1_IN15B);
GLB_A1_P0 : PGAND4
	PORT MAP (Z0 => A1_P0, A3 => A1_IN9, A2 => A1_IN10, A1 => A1_IN13B, 
	A0 => A1_IN16);
GLB_A1_G3 : PGBUFI
	PORT MAP (Z0 => A1_G3, A0 => A1_F5);
GLB_A1_G2 : PGBUFI
	PORT MAP (Z0 => A1_G2, A0 => A1_F0);
GLB_A1_G1 : PGBUFI
	PORT MAP (Z0 => A1_G1, A0 => A1_F4);
GLB_A1_G0 : PGBUFI
	PORT MAP (Z0 => A1_G0, A0 => GND);
GLB_A1_F5 : PGORF76
	PORT MAP (Z0 => A1_F5, A5 => A1_P13, A4 => A1_P14, A3 => A1_P15, 
	A2 => A1_P16, A1 => A1_P17, A0 => A1_P18);
GLB_A1_F4 : PGORF72
	PORT MAP (Z0 => A1_F4, A1 => A1_P11, A0 => A1_P12);
GLB_A1_F1 : PGORF73
	PORT MAP (Z0 => A1_F1, A2 => A1_P5, A1 => A1_P6, A0 => A1_P7);
GLB_A1_F0 : PGORF74
	PORT MAP (Z0 => A1_F0, A3 => A1_P0, A2 => A1_P1, A1 => A1_P2, 
	A0 => A1_P3);
GLB_A1_CLK : PGBUFI
	PORT MAP (Z0 => A1_CLK, A0 => CARRY_ck1f);
GLB_VCC_1283 : PGBUFI
	PORT MAP (Z0 => VCC_1283, A0 => A1_X3O);
GLB_A1_X1MO : PGBUFI
	PORT MAP (Z0 => A1_X1MO, A0 => A1_G1);
GLB_N_145_I : PGBUFI
	PORT MAP (Z0 => N_145_I, A0 => A1_X1O);
GLB_N_155_I : PGBUFI
	PORT MAP (Z0 => N_155_I, A0 => A1_X0O);
GLB_A1_IN8 : PGBUFI
	PORT MAP (Z0 => A1_IN8, A0 => UQNNONMCK_115);
GLB_A1_IN15 : PGBUFI
	PORT MAP (Z0 => A1_IN15, A0 => UQNNONMCK_120);
GLB_A1_IN14 : PGBUFI
	PORT MAP (Z0 => A1_IN14, A0 => UQNNONMCK_118);
GLB_A1_IN12 : PGBUFI
	PORT MAP (Z0 => A1_IN12, A0 => UQNNONMCK_117);
GLB_A1_IN13 : PGBUFI
	PORT MAP (Z0 => A1_IN13, A0 => UQNNONMCK_121);
GLB_A1_IN11 : PGBUFI
	PORT MAP (Z0 => A1_IN11, A0 => UQNNONMCK_119);
GLB_A1_IN16 : PGBUFI
	PORT MAP (Z0 => A1_IN16, A0 => UQNNONMCK_130);
GLB_A1_IN10 : PGBUFI
	PORT MAP (Z0 => A1_IN10, A0 => UQNNONMCK_116);
GLB_A1_IN9 : PGBUFI
	PORT MAP (Z0 => A1_IN9, A0 => UQNNONMCK_114);
GLB_A1_X3O : PGXOR2
	PORT MAP (Z0 => A1_X3O, A1 => VCC, A0 => A1_G0);
GLB_A1_X1O : PGXOR2
	PORT MAP (Z0 => A1_X1O, A1 => A1_X1MO, A0 => A1_G2);
GLB_A1_X0O : PGXOR2
	PORT MAP (Z0 => A1_X0O, A1 => GND, A0 => A1_G3);
UQBNONMCK_100 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_129, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => A1_CLK, 
	D0 => A1_F1);
GLB_A1_IN11B : PGINVI
	PORT MAP (ZN0 => A1_IN11B, A0 => UQNNONMCK_119);
GLB_A1_IN8B : PGINVI
	PORT MAP (ZN0 => A1_IN8B, A0 => UQNNONMCK_115);
GLB_A1_IN12B : PGINVI
	PORT MAP (ZN0 => A1_IN12B, A0 => UQNNONMCK_117);
GLB_A1_IN10B : PGINVI
	PORT MAP (ZN0 => A1_IN10B, A0 => UQNNONMCK_116);
GLB_A1_IN16B : PGINVI
	PORT MAP (ZN0 => A1_IN16B, A0 => UQNNONMCK_130);
GLB_A1_IN4B : PGINVI
	PORT MAP (ZN0 => A1_IN4B, A0 => LOAD_grpi);
GLB_A1_IN9B : PGINVI
	PORT MAP (ZN0 => A1_IN9B, A0 => UQNNONMCK_114);
GLB_A1_IN15B : PGINVI
	PORT MAP (ZN0 => A1_IN15B, A0 => UQNNONMCK_120);
GLB_A1_IN14B : PGINVI
	PORT MAP (ZN0 => A1_IN14B, A0 => UQNNONMCK_118);
GLB_A1_IN13B : PGINVI
	PORT MAP (ZN0 => A1_IN13B, A0 => UQNNONMCK_121);
GLB_A2_P16 : PGAND2
	PORT MAP (Z0 => A2_P16, A1 => A2_IN3, A0 => A2_IN5B);
GLB_A2_P15 : PGAND2
	PORT MAP (Z0 => A2_P15, A1 => A2_IN3, A0 => A2_IN16B);
GLB_A2_P14 : PGAND3
	PORT MAP (Z0 => A2_P14, A2 => A2_IN3B, A1 => A2_IN5, A0 => A2_IN16);
GLB_A2_P11 : PGAND2
	PORT MAP (Z0 => A2_P11, A1 => A2_IN5B, A0 => A2_IN16);
GLB_A2_P10 : PGAND2
	PORT MAP (Z0 => A2_P10, A1 => A2_IN5, A0 => A2_IN16B);
GLB_A2_F3 : PGORF73
	PORT MAP (Z0 => A2_F3, A2 => A2_P14, A1 => A2_P15, A0 => A2_P16);
GLB_A2_F2 : PGORF72
	PORT MAP (Z0 => A2_F2, A1 => A2_P10, A0 => A2_P11);
GLB_A2_CLK : PGBUFI
	PORT MAP (Z0 => A2_CLK, A0 => CLKX_clk0);
GLB_A2_IN3 : PGBUFI
	PORT MAP (Z0 => A2_IN3, A0 => UQNNONMCK_122);
GLB_A2_IN16 : PGBUFI
	PORT MAP (Z0 => A2_IN16, A0 => UQNNONMCK_133);
GLB_A2_IN5 : PGBUFI
	PORT MAP (Z0 => A2_IN5, A0 => UQNNONMCK_124);
UQBNONMCK_101 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_131, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => A2_CLK, 
	D0 => A2_F2);
UQBNONMCK_102 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_132, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => A2_CLK, 
	D0 => A2_F3);
GLB_A2_IN3B : PGINVI
	PORT MAP (ZN0 => A2_IN3B, A0 => UQNNONMCK_122);
GLB_A2_IN5B : PGINVI
	PORT MAP (ZN0 => A2_IN5B, A0 => UQNNONMCK_124);
GLB_A2_IN16B : PGINVI
	PORT MAP (ZN0 => A2_IN16B, A0 => UQNNONMCK_133);
GLB_A6_P13 : PGAND2
	PORT MAP (Z0 => A6_P13, A1 => A6_IN8, A0 => A6_IN9);
GLB_A6_P8 : PGAND2
	PORT MAP (Z0 => A6_P8, A1 => A6_IN8, A0 => A6_IN9B);
GLB_A6_P4 : PGAND2
	PORT MAP (Z0 => A6_P4, A1 => A6_IN8B, A0 => A6_IN9);
GLB_A6_P0 : PGAND2
	PORT MAP (Z0 => A6_P0, A1 => A6_IN8B, A0 => A6_IN9B);
GLB_A6_G3 : PGBUFI
	PORT MAP (Z0 => A6_G3, A0 => GND);
GLB_A6_G2 : PGBUFI
	PORT MAP (Z0 => A6_G2, A0 => GND);
GLB_A6_G1 : PGBUFI
	PORT MAP (Z0 => A6_G1, A0 => GND);
GLB_A6_G0 : PGBUFI
	PORT MAP (Z0 => A6_G0, A0 => GND);
GLB_A6_P0_xa : PGBUFI
	PORT MAP (Z0 => A6_P0_xa, A0 => A6_P0);
GLB_AND_1070 : PGBUFI
	PORT MAP (Z0 => AND_1070, A0 => A6_X3O);
GLB_A6_P4_xa : PGBUFI
	PORT MAP (Z0 => A6_P4_xa, A0 => A6_P4);
GLB_AND_1068 : PGBUFI
	PORT MAP (Z0 => AND_1068, A0 => A6_X2O);
GLB_A6_P8_xa : PGBUFI
	PORT MAP (Z0 => A6_P8_xa, A0 => A6_P8);
GLB_AND_1069 : PGBUFI
	PORT MAP (Z0 => AND_1069, A0 => A6_X1O);
GLB_A6_P13_xa : PGBUFI
	PORT MAP (Z0 => A6_P13_xa, A0 => A6_P13);
GLB_AND_1071 : PGBUFI
	PORT MAP (Z0 => AND_1071, A0 => A6_X0O);
GLB_A6_IN8 : PGBUFI
	PORT MAP (Z0 => A6_IN8, A0 => UQNNONMCK_125);
GLB_A6_IN9 : PGBUFI
	PORT MAP (Z0 => A6_IN9, A0 => UQNNONMCK_121);
GLB_A6_X3O : PGXOR2
	PORT MAP (Z0 => A6_X3O, A1 => A6_P0_xa, A0 => A6_G0);
GLB_A6_X2O : PGXOR2
	PORT MAP (Z0 => A6_X2O, A1 => A6_P4_xa, A0 => A6_G1);
GLB_A6_X1O : PGXOR2
	PORT MAP (Z0 => A6_X1O, A1 => A6_P8_xa, A0 => A6_G2);
GLB_A6_X0O : PGXOR2
	PORT MAP (Z0 => A6_X0O, A1 => A6_P13_xa, A0 => A6_G3);
GLB_A6_IN9B : PGINVI
	PORT MAP (ZN0 => A6_IN9B, A0 => UQNNONMCK_121);
GLB_A6_IN8B : PGINVI
	PORT MAP (ZN0 => A6_IN8B, A0 => UQNNONMCK_125);
GLB_B0_P13 : PGBUFI
	PORT MAP (Z0 => B0_P13, A0 => B0_IN8);
GLB_B0_P8 : PGBUFI
	PORT MAP (Z0 => B0_P8, A0 => B0_IN9);
GLB_B0_P4 : PGBUFI
	PORT MAP (Z0 => B0_P4, A0 => B0_IN10);
GLB_B0_P0 : PGBUFI
	PORT MAP (Z0 => B0_P0, A0 => B0_IN11);
GLB_B0_G3 : PGBUFI
	PORT MAP (Z0 => B0_G3, A0 => GND);
GLB_B0_G2 : PGBUFI
	PORT MAP (Z0 => B0_G2, A0 => GND);
GLB_B0_G1 : PGBUFI
	PORT MAP (Z0 => B0_G1, A0 => GND);
GLB_B0_G0 : PGBUFI
	PORT MAP (Z0 => B0_G0, A0 => GND);
GLB_B0_P0_xa : PGBUFI
	PORT MAP (Z0 => B0_P0_xa, A0 => B0_P0);
GLB_AND_1070_buff1 : PGBUFI
	PORT MAP (Z0 => AND_1070_buff1, A0 => B0_X3O);
GLB_B0_P4_xa : PGBUFI
	PORT MAP (Z0 => B0_P4_xa, A0 => B0_P4);
GLB_AND_1068_buff1 : PGBUFI
	PORT MAP (Z0 => AND_1068_buff1, A0 => B0_X2O);
GLB_B0_P8_xa : PGBUFI
	PORT MAP (Z0 => B0_P8_xa, A0 => B0_P8);
GLB_AND_1069_buff1 : PGBUFI
	PORT MAP (Z0 => AND_1069_buff1, A0 => B0_X1O);
GLB_B0_P13_xa : PGBUFI
	PORT MAP (Z0 => B0_P13_xa, A0 => B0_P13);
GLB_AND_1071_buff1 : PGBUFI
	PORT MAP (Z0 => AND_1071_buff1, A0 => B0_X0O);
GLB_B0_IN8 : PGBUFI
	PORT MAP (Z0 => B0_IN8, A0 => AND_1071_grpi);
GLB_B0_IN9 : PGBUFI
	PORT MAP (Z0 => B0_IN9, A0 => AND_1069_grpi);
GLB_B0_IN10 : PGBUFI
	PORT MAP (Z0 => B0_IN10, A0 => AND_1068_grpi);
GLB_B0_IN11 : PGBUFI
	PORT MAP (Z0 => B0_IN11, A0 => AND_1070_grpi);
GLB_B0_X3O : PGXOR2
	PORT MAP (Z0 => B0_X3O, A1 => B0_P0_xa, A0 => B0_G0);
GLB_B0_X2O : PGXOR2
	PORT MAP (Z0 => B0_X2O, A1 => B0_P4_xa, A0 => B0_G1);
GLB_B0_X1O : PGXOR2
	PORT MAP (Z0 => B0_X1O, A1 => B0_P8_xa, A0 => B0_G2);
GLB_B0_X0O : PGXOR2
	PORT MAP (Z0 => B0_X0O, A1 => B0_P13_xa, A0 => B0_G3);
GLB_B3_P16 : PGAND2
	PORT MAP (Z0 => B3_P16, A1 => B3_IN8, A0 => B3_IN16B);
GLB_B3_P15 : PGAND2
	PORT MAP (Z0 => B3_P15, A1 => B3_IN8B, A0 => B3_IN16);
GLB_B3_P8 : PGBUFI
	PORT MAP (Z0 => B3_P8, A0 => B3_IN16B);
GLB_B3_G2 : PGBUFI
	PORT MAP (Z0 => B3_G2, A0 => GND);
GLB_B3_F3 : PGORF72
	PORT MAP (Z0 => B3_F3, A1 => B3_P15, A0 => B3_P16);
GLB_B3_CLK : PGBUFI
	PORT MAP (Z0 => B3_CLK, A0 => CLK1X_clk2);
GLB_B3_P8_xa : PGBUFI
	PORT MAP (Z0 => B3_P8_xa, A0 => B3_P8);
GLB_B3_IN8 : PGBUFI
	PORT MAP (Z0 => B3_IN8, A0 => UQNNONMCK_125);
GLB_B3_IN16 : PGBUFI
	PORT MAP (Z0 => B3_IN16, A0 => UQNNONMCK_136);
GLB_B3_X1O : PGXOR2
	PORT MAP (Z0 => B3_X1O, A1 => B3_P8_xa, A0 => B3_G2);
UQBNONMCK_103 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_134, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => B3_CLK, 
	D0 => B3_X1O);
UQBNONMCK_104 : PGDFFR
	PORT MAP (Q0 => UQNNONMCK_135, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => B3_CLK, 
	D0 => B3_F3);
GLB_B3_IN8B : PGINVI
	PORT MAP (ZN0 => B3_IN8B, A0 => UQNNONMCK_125);
GLB_B3_IN16B : PGINVI
	PORT MAP (ZN0 => B3_IN16B, A0 => UQNNONMCK_136);
GLB_C0_P13 : PGAND3
	PORT MAP (Z0 => C0_P13, A2 => C0_IN10, A1 => C0_IN12, A0 => C0_IN13);
GLB_C0_P8 : PGAND2
	PORT MAP (Z0 => C0_P8, A1 => C0_IN4, A0 => C0_IN8);
GLB_C0_P4 : PGAND2
	PORT MAP (Z0 => C0_P4, A1 => C0_IN4B, A0 => C0_IN8);
GLB_C0_P0 : PGAND2
	PORT MAP (Z0 => C0_P0, A1 => C0_IN4B, A0 => C0_IN8B);
GLB_C0_G3 : PGBUFI
	PORT MAP (Z0 => C0_G3, A0 => GND);
GLB_C0_G2 : PGBUFI
	PORT MAP (Z0 => C0_G2, A0 => GND);
GLB_C0_G1 : PGBUFI
	PORT MAP (Z0 => C0_G1, A0 => GND);
GLB_C0_G0 : PGBUFI
	PORT MAP (Z0 => C0_G0, A0 => GND);
GLB_C0_CLK : PGBUFI
	PORT MAP (Z0 => C0_CLK, A0 => CLKX_clk0);
GLB_C0_P0_xa : PGBUFI
	PORT MAP (Z0 => C0_P0_xa, A0 => C0_P0);
GLB_AND_1073 : PGBUFI
	PORT MAP (Z0 => AND_1073, A0 => C0_X3O);
GLB_C0_P4_xa : PGBUFI
	PORT MAP (Z0 => C0_P4_xa, A0 => C0_P4);
GLB_AND_1074 : PGBUFI
	PORT MAP (Z0 => AND_1074, A0 => C0_X2O);
GLB_C0_P8_xa : PGBUFI
	PORT MAP (Z0 => C0_P8_xa, A0 => C0_P8);
GLB_AND_1072 : PGBUFI
	PORT MAP (Z0 => AND_1072, A0 => C0_X1O);
GLB_C0_P13_xa : PGBUFI
	PORT MAP (Z0 => C0_P13_xa, A0 => C0_P13);
GLB_C0_IN13 : PGBUFI
	PORT MAP (Z0 => C0_IN13, A0 => UQNNONMCK_123);
GLB_C0_IN12 : PGBUFI
	PORT MAP (Z0 => C0_IN12, A0 => UQNNONMCK_122);
GLB_C0_IN10 : PGBUFI
	PORT MAP (Z0 => C0_IN10, A0 => UQNNONMCK_124);
GLB_C0_IN4 : PGBUFI
	PORT MAP (Z0 => C0_IN4, A0 => UQNNONMCK_112);
GLB_C0_IN8 : PGBUFI
	PORT MAP (Z0 => C0_IN8, A0 => UQNNONMCK_126);
GLB_C0_X3O : PGXOR2
	PORT MAP (Z0 => C0_X3O, A1 => C0_P0_xa, A0 => C0_G0);
GLB_C0_X2O : PGXOR2
	PORT MAP (Z0 => C0_X2O, A1 => C0_P4_xa, A0 => C0_G1);
GLB_C0_X1O : PGXOR2
	PORT MAP (Z0 => C0_X1O, A1 => C0_P8_xa, A0 => C0_G2);
GLB_C0_X0O : PGXOR2
	PORT MAP (Z0 => C0_X0O, A1 => C0_P13_xa, A0 => C0_G3);
GLB_CARRY : PGDFFR
	PORT MAP (Q0 => CARRY, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => C0_CLK, 
	D0 => C0_X0O);
GLB_C0_IN8B : PGINVI
	PORT MAP (ZN0 => C0_IN8B, A0 => UQNNONMCK_126);
GLB_C0_IN4B : PGINVI
	PORT MAP (ZN0 => C0_IN4B, A0 => UQNNONMCK_112);
GLB_C3_P13 : PGAND9
	PORT MAP (Z0 => C3_P13, A8 => C3_IN0B, A7 => C3_IN1B, A6 => C3_IN3B, 
	A5 => C3_IN4B, A4 => C3_IN5B, A3 => C3_IN6B, A2 => C3_IN7B, 
	A1 => C3_IN8B, A0 => C3_IN9B);
GLB_C3_P8 : PGAND4
	PORT MAP (Z0 => C3_P8, A3 => C3_IN5B, A2 => C3_IN6B, A1 => C3_IN7B, 
	A0 => C3_IN9B);
GLB_C3_P7 : PGBUFI
	PORT MAP (Z0 => C3_P7, A0 => C3_IN17);
GLB_C3_P4 : PGAND2
	PORT MAP (Z0 => C3_P4, A1 => C3_IN8B, A0 => C3_IN17);
GLB_C3_P3 : PGBUFI
	PORT MAP (Z0 => C3_P3, A0 => C3_IN17);
GLB_C3_P0 : PGAND9
	PORT MAP (Z0 => C3_P0, A8 => C3_IN0B, A7 => C3_IN1B, A6 => C3_IN3B, 
	A5 => C3_IN4B, A4 => C3_IN5B, A3 => C3_IN6B, A2 => C3_IN7B, 
	A1 => C3_IN8B, A0 => C3_IN9B);
GLB_C3_G3 : PGBUFI
	PORT MAP (Z0 => C3_G3, A0 => C3_F0);
GLB_C3_G2 : PGBUFI
	PORT MAP (Z0 => C3_G2, A0 => GND);
GLB_C3_G1 : PGBUFI
	PORT MAP (Z0 => C3_G1, A0 => GND);
GLB_C3_G0 : PGBUFI
	PORT MAP (Z0 => C3_G0, A0 => C3_F1);
GLB_C3_F1 : PGBUFI
	PORT MAP (Z0 => C3_F1, A0 => C3_P7);
GLB_C3_F0 : PGBUFI
	PORT MAP (Z0 => C3_F0, A0 => C3_P3);
GLB_C3_P0_xa : PGBUFI
	PORT MAP (Z0 => C3_P0_xa, A0 => C3_P0);
GLB_C3_P4_xa : PGBUFI
	PORT MAP (Z0 => C3_P4_xa, A0 => C3_P4);
GLB_AND_1075 : PGBUFI
	PORT MAP (Z0 => AND_1075, A0 => C3_X2O);
GLB_C3_P8_xa : PGBUFI
	PORT MAP (Z0 => C3_P8_xa, A0 => C3_P8);
GLB_UQNN_N6 : PGBUFI
	PORT MAP (Z0 => UQNN_N6, A0 => C3_X1O);
GLB_C3_P13_xa : PGBUFI
	PORT MAP (Z0 => C3_P13_xa, A0 => C3_P13);
GLB_C3_IN17 : PGBUFI
	PORT MAP (Z0 => C3_IN17, A0 => UQNNONMCK_138);
GLB_C3_X3O : PGXOR2
	PORT MAP (Z0 => C3_X3O, A1 => C3_P0_xa, A0 => C3_G0);
GLB_C3_X2O : PGXOR2
	PORT MAP (Z0 => C3_X2O, A1 => C3_P4_xa, A0 => C3_G1);
GLB_C3_X1O : PGXOR2
	PORT MAP (Z0 => C3_X1O, A1 => C3_P8_xa, A0 => C3_G2);
GLB_C3_X0O : PGXOR2
	PORT MAP (Z0 => C3_X0O, A1 => C3_P13_xa, A0 => C3_G3);