trafic.sim

CPLD lattice1032 VHDL实现交通灯控制！

   SYM PGORF72 GLB_B3_F3 GLB glb08;
      PIN  Z0  OUT  B3_F3;
      PIN  A1  IN  B3_P15;
      PIN  A0  IN  B3_P16;
   END;  // SYM PGORFB2

   SYM PGBUFI GLB_B3_CLK GLB glb08;
      PIN  Z0  OUT  B3_CLK;
      PIN  A0  IN  CLK1X_clk2;
   END;  // SYM PGBUFK

   SYM PGBUFI GLB_B3_P8_xa GLB glb08;
      PIN  Z0  OUT  B3_P8_xa;
      PIN  A0  IN  B3_P8;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_B3_IN8 GLB glb08;
      PIN  Z0  OUT  B3_IN8;
      PIN  A0  IN  COUNTA%1%_grpi;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_B3_IN16 GLB glb08;
      PIN  Z0  OUT  B3_IN16;
      PIN  A0  IN  COUNTA%0%_ffb;
   END;  // SYM PGBUFI

   SYM PGXOR2 GLB_B3_X1O GLB glb08;
      PIN  Z0  OUT  B3_X1O;
      PIN  A1  IN  B3_P8_xa;
      PIN  A0  IN  B3_G2;
   END;  // SYM PGXOR2

   SYM PGDFFR GLB_COUNTA%0% GLB glb08;
      PIN  Q0  OUT  COUNTA%0%;
      PIN  RNESET  IN  L2L_KEYWD_RESET_glbb;
      PIN  CD  IN  GND;
      PIN  CLK  IN  B3_CLK;
      PIN  D0  IN  B3_X1O;
   END;  // SYM PGDFFR

   SYM PGDFFR GLB_COUNTA%1% GLB glb08;
      PIN  Q0  OUT  COUNTA%1%;
      PIN  RNESET  IN  L2L_KEYWD_RESET_glbb;
      PIN  CD  IN  GND;
      PIN  CLK  IN  B3_CLK;
      PIN  D0  IN  B3_F3;
   END;  // SYM PGDFFR

   SYM PGINVI GLB_B3_IN8B GLB glb08;
      PIN  ZN0  OUT  B3_IN8B;
      PIN  A0  IN  COUNTA%1%_grpi;
   END;  // SYM PGINVI

   SYM PGINVI GLB_B3_IN16B GLB glb08;
      PIN  ZN0  OUT  B3_IN16B;
      PIN  A0  IN  COUNTA%0%_ffb;
   END;  // SYM PGINVI

   SYM PGAND3 GLB_C0_P13 GLB glb01;
      PIN  Z0  OUT  C0_P13;
      PIN  A2  IN  C0_IN10;
      PIN  A1  IN  C0_IN12;
      PIN  A0  IN  C0_IN13;
   END;  // SYM PGANDD3

   SYM PGAND2 GLB_C0_P8 GLB glb01;
      PIN  Z0  OUT  C0_P8;
      PIN  A1  IN  C0_IN4;
      PIN  A0  IN  C0_IN8;
   END;  // SYM PGANDD2

   SYM PGAND2 GLB_C0_P4 GLB glb01;
      PIN  Z0  OUT  C0_P4;
      PIN  A1  IN  C0_IN4B;
      PIN  A0  IN  C0_IN8;
   END;  // SYM PGANDD2

   SYM PGAND2 GLB_C0_P0 GLB glb01;
      PIN  Z0  OUT  C0_P0;
      PIN  A1  IN  C0_IN4B;
      PIN  A0  IN  C0_IN8B;
   END;  // SYM PGANDD2

   SYM PGBUFI GLB_C0_G3 GLB glb01;
      PIN  Z0  OUT  C0_G3;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C0_G2 GLB glb01;
      PIN  Z0  OUT  C0_G2;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C0_G1 GLB glb01;
      PIN  Z0  OUT  C0_G1;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C0_G0 GLB glb01;
      PIN  Z0  OUT  C0_G0;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C0_CLK GLB glb01;
      PIN  Z0  OUT  C0_CLK;
      PIN  A0  IN  CLKX_clk0;
   END;  // SYM PGBUFK

   SYM PGBUFI GLB_C0_P0_xa GLB glb01;
      PIN  Z0  OUT  C0_P0_xa;
      PIN  A0  IN  C0_P0;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_AND_1073 GLB glb01;
      PIN  Z0  OUT  AND_1073;
      PIN  A0  IN  C0_X3O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_C0_P4_xa GLB glb01;
      PIN  Z0  OUT  C0_P4_xa;
      PIN  A0  IN  C0_P4;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_AND_1074 GLB glb01;
      PIN  Z0  OUT  AND_1074;
      PIN  A0  IN  C0_X2O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_C0_P8_xa GLB glb01;
      PIN  Z0  OUT  C0_P8_xa;
      PIN  A0  IN  C0_P8;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_AND_1072 GLB glb01;
      PIN  Z0  OUT  AND_1072;
      PIN  A0  IN  C0_X1O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_C0_P13_xa GLB glb01;
      PIN  Z0  OUT  C0_P13_xa;
      PIN  A0  IN  C0_P13;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_C0_IN13 GLB glb01;
      PIN  Z0  OUT  C0_IN13;
      PIN  A0  IN  COUNT%1%_grpi;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_C0_IN12 GLB glb01;
      PIN  Z0  OUT  C0_IN12;
      PIN  A0  IN  COUNT%2%_grpi;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_C0_IN10 GLB glb01;
      PIN  Z0  OUT  C0_IN10;
      PIN  A0  IN  COUNT%0%_grpi;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_C0_IN4 GLB glb01;
      PIN  Z0  OUT  C0_IN4;
      PIN  A0  IN  STATE_C%1%_grpi;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_C0_IN8 GLB glb01;
      PIN  Z0  OUT  C0_IN8;
      PIN  A0  IN  STATE%0%_grpi;
   END;  // SYM PGBUFI

   SYM PGXOR2 GLB_C0_X3O GLB glb01;
      PIN  Z0  OUT  C0_X3O;
      PIN  A1  IN  C0_P0_xa;
      PIN  A0  IN  C0_G0;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_C0_X2O GLB glb01;
      PIN  Z0  OUT  C0_X2O;
      PIN  A1  IN  C0_P4_xa;
      PIN  A0  IN  C0_G1;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_C0_X1O GLB glb01;
      PIN  Z0  OUT  C0_X1O;
      PIN  A1  IN  C0_P8_xa;
      PIN  A0  IN  C0_G2;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_C0_X0O GLB glb01;
      PIN  Z0  OUT  C0_X0O;
      PIN  A1  IN  C0_P13_xa;
      PIN  A0  IN  C0_G3;
   END;  // SYM PGXOR2

   SYM PGDFFR GLB_CARRY GLB glb01;
      PIN  Q0  OUT  CARRY;
      PIN  RNESET  IN  L2L_KEYWD_RESET_glbb;
      PIN  CD  IN  GND;
      PIN  CLK  IN  C0_CLK;
      PIN  D0  IN  C0_X0O;
   END;  // SYM PGDFFR

   SYM PGINVI GLB_C0_IN8B GLB glb01;
      PIN  ZN0  OUT  C0_IN8B;
      PIN  A0  IN  STATE%0%_grpi;
   END;  // SYM PGINVI

   SYM PGINVI GLB_C0_IN4B GLB glb01;
      PIN  ZN0  OUT  C0_IN4B;
      PIN  A0  IN  STATE_C%1%_grpi;
   END;  // SYM PGINVI

   SYM PGAND9 GLB_C3_P13 GLB glb02;
      PIN  Z0  OUT  C3_P13;
      PIN  A8  IN  C3_IN0B;
      PIN  A7  IN  C3_IN1B;
      PIN  A6  IN  C3_IN3B;
      PIN  A5  IN  C3_IN4B;
      PIN  A4  IN  C3_IN5B;
      PIN  A3  IN  C3_IN6B;
      PIN  A2  IN  C3_IN7B;
      PIN  A1  IN  C3_IN8B;
      PIN  A0  IN  C3_IN9B;
   END;  // SYM PGANDD9

   SYM PGAND4 GLB_C3_P8 GLB glb02;
      PIN  Z0  OUT  C3_P8;
      PIN  A3  IN  C3_IN5B;
      PIN  A2  IN  C3_IN6B;
      PIN  A1  IN  C3_IN7B;
      PIN  A0  IN  C3_IN9B;
   END;  // SYM PGANDD4

   SYM PGBUFI GLB_C3_P7 GLB glb02;
      PIN  Z0  OUT  C3_P7;
      PIN  A0  IN  C3_IN17;
   END;  // SYM PGAND1

   SYM PGAND2 GLB_C3_P4 GLB glb02;
      PIN  Z0  OUT  C3_P4;
      PIN  A1  IN  C3_IN8B;
      PIN  A0  IN  C3_IN17;
   END;  // SYM PGANDD2

   SYM PGBUFI GLB_C3_P3 GLB glb02;
      PIN  Z0  OUT  C3_P3;
      PIN  A0  IN  C3_IN17;
   END;  // SYM PGAND1

   SYM PGAND9 GLB_C3_P0 GLB glb02;
      PIN  Z0  OUT  C3_P0;
      PIN  A8  IN  C3_IN0B;
      PIN  A7  IN  C3_IN1B;
      PIN  A6  IN  C3_IN3B;
      PIN  A5  IN  C3_IN4B;
      PIN  A4  IN  C3_IN5B;
      PIN  A3  IN  C3_IN6B;
      PIN  A2  IN  C3_IN7B;
      PIN  A1  IN  C3_IN8B;
      PIN  A0  IN  C3_IN9B;
   END;  // SYM PGANDD9

   SYM PGBUFI GLB_C3_G3 GLB glb02;
      PIN  Z0  OUT  C3_G3;
      PIN  A0  IN  C3_F0;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C3_G2 GLB glb02;
      PIN  Z0  OUT  C3_G2;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C3_G1 GLB glb02;
      PIN  Z0  OUT  C3_G1;
      PIN  A0  IN  GND;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C3_G0 GLB glb02;
      PIN  Z0  OUT  C3_G0;
      PIN  A0  IN  C3_F1;
   END;  // SYM PGORG1

   SYM PGBUFI GLB_C3_F1 GLB glb02;
      PIN  Z0  OUT  C3_F1;
      PIN  A0  IN  C3_P7;
   END;  // SYM PGORF41

   SYM PGBUFI GLB_C3_F0 GLB glb02;
      PIN  Z0  OUT  C3_F0;
      PIN  A0  IN  C3_P3;
   END;  // SYM PGORF41

   SYM PGBUFI GLB_C3_P0_xa GLB glb02;
      PIN  Z0  OUT  C3_P0_xa;
      PIN  A0  IN  C3_P0;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_C3_P4_xa GLB glb02;
      PIN  Z0  OUT  C3_P4_xa;
      PIN  A0  IN  C3_P4;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_AND_1075 GLB glb02;
      PIN  Z0  OUT  AND_1075;
      PIN  A0  IN  C3_X2O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_C3_P8_xa GLB glb02;
      PIN  Z0  OUT  C3_P8_xa;
      PIN  A0  IN  C3_P8;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_UQNN_N6 GLB glb02;
      PIN  Z0  OUT  UQNN_N6;
      PIN  A0  IN  C3_X1O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_C3_P13_xa GLB glb02;
      PIN  Z0  OUT  C3_P13_xa;
      PIN  A0  IN  C3_P13;
   END;  // SYM PGBUFXA

   SYM PGBUFI GLB_C3_IN17 GLB glb02;
      PIN  Z0  OUT  C3_IN17;
      PIN  A0  IN  STATE_C%1%_ffb;
   END;  // SYM PGBUFI

   SYM PGXOR2 GLB_C3_X3O GLB glb02;
      PIN  Z0  OUT  C3_X3O;
      PIN  A1  IN  C3