trafic.vm

CPLD lattice1032 VHDL实现交通灯控制！

//
// Written by Synplify
// Synplify 7.2, Build 184R.
// Thu Dec 06 09:08:46 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools3\synpbase\lib\vhd\std.vhd "
// file 2 "\e:\edapro~2\pt1032e\trafic\trafic.vhd "
// file 3 "\d:\isptools3\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\isptools3\synpbase\lib\vhd\unsigned.vhd "
// file 5 "\d:\isptools3\synpbase\lib\vhd\arith.vhd "

`timescale 100 ps/100 ps
module DFF_FD (
  Q,
  D,
  CP,
  R
);
output Q;
input D;
input CP;
input R;
wire Q ;
wire D ;
wire CP ;
wire R ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  reg Q_r_e_g; // dffr
  always @(posedge CP or posedge R ) Q_r_e_g = #1 R ? 1'b0 : D ;
    assign Q = Q_r_e_g;
endmodule /* DFF_FD */

module FD11 (
  Q0,
  D0,
  CLK
);
output Q0;
input D0;
input CLK;
wire Q0 ;
wire D0 ;
wire CLK ;
wire VCC ;
wire GND ;
  DFF_FD blk2 (
	.Q(Q0),
	.D(D0),
	.CP(CLK),
	.R(GND)
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* FD11 */

module XOR2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  Z0 = A0  ^ A1 ;
endmodule /* XOR2 */

module AND2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  Z0 = A0  & A1 ;
endmodule /* AND2 */

module XINPUT (
  Z0,
  XI0
);
output Z0;
input XI0;
wire Z0 ;
wire XI0 ;
wire VCC ;
wire GND ;
  assign #(1)  Z0 = XI0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* XINPUT */

module IB11 (
  Z0,
  XI0
);
output Z0;
input XI0;
wire Z0 ;
wire XI0 ;
wire VCC ;
wire GND ;
  XINPUT \\$1I45  (
	.Z0(Z0),
	.XI0(XI0)
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* IB11 */

module XOUTPUT (
  XO0,
  A0
);
output XO0;
input A0;
wire XO0 ;
wire A0 ;
wire VCC ;
wire GND ;
  assign #(1)  XO0 = A0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* XOUTPUT */

module OB11 (
  XO0,
  A0
);
output XO0;
input A0;
wire XO0 ;
wire A0 ;
wire VCC ;
wire GND ;
  XOUTPUT \\$1I42  (
	.XO0(XO0),
	.A0(A0)
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* OB11 */

module INV (
  ZN0,
  A0
);
output ZN0;
input A0;
wire ZN0 ;
wire A0 ;
wire VCC ;
wire GND ;
  assign #(1)  ZN0 = ~ A0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* INV */

module OR2 (
  Z0,
  A0,
  A1
);
output Z0;
input A0;
input A1;
wire Z0 ;
wire A0 ;
wire A1 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  Z0 = A0  | A1 ;
endmodule /* OR2 */

module MUX2 (
  Z0,
  A0,
  A1,
  S0
);
output Z0;
input A0;
input A1;
input S0;
wire Z0 ;
wire A0 ;
wire A1 ;
wire S0 ;
wire \$1N8  ;
wire \$1N22  ;
wire \$1N6  ;
wire VCC ;
wire GND ;
  AND2 \\$1I25  (
	.Z0(\$1N6 ),
	.A0(A0),
	.A1(\$1N22 )
);
  AND2 \\$1I31  (
	.Z0(\$1N8 ),
	.A0(A1),
	.A1(S0)
);
  OR2 \\$1I35  (
	.Z0(Z0),
	.A0(\$1N6 ),
	.A1(\$1N8 )
);
  INV \\$1I38  (
	.ZN0(\$1N22 ),
	.A0(S0)
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* MUX2 */

module OR3 (
  Z0,
  A0,
  A1,
  A2
);
output Z0;
input A0;
input A1;
input A2;
wire Z0 ;
wire A0 ;
wire A1 ;
wire A2 ;
wire VCC ;
wire GND ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
  assign #(1)  Z0 = A0  | A1  | A2 ;
endmodule /* OR3 */

module BUF (
  Z0,
  A0
);
output Z0;
input A0;
wire Z0 ;
wire A0 ;
wire VCC ;
wire GND ;
  assign #(1)  Z0 = A0;
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* BUF */

module LD11 (
  Q0,
  D0,
  G
);
output Q0;
input D0;
input G;
wire Q0 ;
wire D0 ;
wire G ;
wire \$1N261  ;
wire \$1N188  ;
wire \$1N166  ;
wire \$1N159  ;
wire \$1N6  ;
wire VCC ;
wire GND ;
  OR3 \\$1I186  (
	.Z0(\$1N6 ),
	.A0(\$1N166 ),
	.A1(\$1N159 ),
	.A2(\$1N188 )
);
  AND2 \\$1I254  (
	.Z0(\$1N166 ),
	.A0(\$1N6 ),
	.A1(D0)
);
  AND2 \\$1I257  (
	.Z0(\$1N188 ),
	.A0(D0),
	.A1(G)
);
  AND2 \\$1I258  (
	.Z0(\$1N159 ),
	.A0(\$1N6 ),
	.A1(\$1N261 )
);
  INV \\$1I260  (
	.ZN0(\$1N261 ),
	.A0(G)
);
  BUF \\$1I270  (
	.Z0(Q0),
	.A0(\$1N6 )
);
  assign VCC = 1'b1;
  assign GND = 1'b0;
endmodule /* LD11 */

module trafic (
  clk,
  clk1,
  R1,
  R2,
  Y1,
  Y2,
  G1,
  G2,
  segout,
  selout
);
input clk;
input clk1;
output R1;
output R2;
output Y1;
output Y2;
output G1;
output G2;
output [7:0] segout;
output [3:0] selout;
wire clk ;
wire clk1 ;
wire R1 ;
wire R2 ;
wire Y1 ;
wire Y2 ;
wire G1 ;
wire G2 ;
wire [7:0] segout;
wire [3:0] selout;
wire [1:0] counta;
wire [3:0] count0;
wire [3:0] count1;
wire [0:0] state;
wire [2:0] count;
wire [3:0] temp;
wire [2:1] un6_counta;
wire [1:1] next_state;
wire [1:1] state_c;
wire [2:1] num_c;
wire [3:0] temp_i;
wire [3:0] count1_i;
wire [3:0] count0_i;
wire [1:1] state_c_i;
wire [0:0] state_i;
wire [1:0] counta_i;
wire [0:0] count_i;
wire carry ;
wire load ;
wire un1_counta ;
wire \p11.un10_count  ;
wire \p6.light9  ;
wire \p6.light10  ;
wire \p6.light11  ;
wire \p6.light12  ;
wire un1_sel ;
wire un3_sel ;
wire un9_sel ;
wire \p2.un2_count0  ;
wire en ;
wire \p4.un22_count0  ;
wire N_5 ;
wire N_6 ;
wire count_n1 ;
wire count_n2 ;
wire count0_n0 ;
wire count0_n1 ;
wire count0_n2 ;
wire count0_n3 ;
wire count1_e0 ;
wire count1_e1 ;
wire count1_e2 ;
wire count1_e3 ;
wire N_80 ;
wire N_96 ;
wire N_102 ;
wire N_103 ;
wire N_104 ;
wire N_105 ;
wire N_106 ;
wire N_107 ;
wire N_108 ;
wire N_109 ;
wire N_110 ;
wire N_111 ;
wire N_112 ;
wire N_113 ;
wire N_114 ;
wire N_115 ;
wire N_116 ;
wire N_118 ;
wire N_119 ;
wire N_120 ;
wire N_123 ;
wire count_c1 ;
wire un1_load_1 ;
wire N_12 ;
wire N_14 ;
wire N_16 ;
wire N_18 ;
wire \p2.un2_count0_1  ;
wire N_24 ;
wire count1_n3 ;
wire N_26 ;
wire count1_n2 ;
wire \p3.un2_count1_1  ;
wire count1_n1 ;
wire N_22 ;
wire count1_n0 ;
wire N_38 ;
wire N_20 ;
wire \p3.un2_count1  ;
wire un1_load_3 ;
wire clk_c ;
wire clk1_c ;
wire VCC ;
wire N_141 ;
wire N_143 ;
wire N_145 ;
wire N_148 ;
wire N_150 ;
wire N_155 ;
wire \p2.un3_count0_i  ;
wire N_13_i_0 ;
wire N_128_i ;
wire N_17_i_0 ;
wire N_25_i_0 ;
wire N_23_i_0 ;
wire N_21_i_0 ;
wire N_19_i ;
wire N_98_i_0 ;
wire N_97_i_0 ;
wire N_175 ;
wire N_176 ;
wire N_177 ;
wire N_178 ;
wire N_179 ;
wire N_180 ;
wire N_181 ;
wire N_182 ;
wire N_183 ;
wire N_184 ;
wire N_185 ;
wire N_186 ;
wire N_187 ;
wire N_188 ;
wire N_189 ;
wire N_190 ;
wire N_191 ;
wire N_192 ;
wire N_193 ;
wire N_108_i ;
wire N_109_i ;
wire N_80_i ;
wire N_107_i ;
wire N_106_i ;
wire N_105_i ;
wire N_120_i ;
wire N_112_i ;
wire N_111_i ;
wire N_102_i ;
wire N_103_i ;
wire N_116_i ;
wire N_114_i ;
wire N_115_i ;
wire N_113_i ;
wire N_104_i ;
wire N_110_i ;
wire N_97_i_0_i ;
wire un1_counta_i ;
wire un9_sel_i ;
wire un3_sel_i ;
wire un1_sel_i ;
wire N_143_i ;
wire N_145_i ;
wire N_150_i ;
wire N_148_i ;
wire N_155_i ;
wire \p6.light11_i  ;
wire \p6.light9_i  ;
wire \p6.light12_i  ;
wire \p6.light10_i  ;
wire load_i ;
wire N_38_i ;
wire \p3.un2_count1_i  ;
wire \p2.un2_count0_i  ;
wire N_141_i ;
wire N_96_i ;
wire N_98_i_0_i ;
wire carry_i ;
wire GND ;
// @2:37
  FD11 \counta_Z[1]  (
	.Q0(counta[1]),
	.D0(un6_counta[1]),
	.CLK(clk1_c)
);
// @2:104
  FD11 \state_Z[0]  (
	.Q0(state[0]),
	.D0(N_5),
	.CLK(carry_i)
);
// @2:104
  FD11 \state[1]  (
	.Q0(state_c[1]),
	.D0(N_6),
	.CLK(carry_i)
);
// @2:91
  FD11 \count1_Z[1]  (
	.Q0(count1[1]),
	.D0(count1_e1),
	.CLK(carry)
);
// @2:91
  FD11 \count1_Z[2]  (
	.Q0(count1[2]),
	.D0(count1_e2),
	.CLK(carry)
);
// @2:91
  FD11 \count1_Z[3]  (
	.Q0(count1[3]),
	.D0(count1_e3),
	.CLK(carry)
);
// @2:37
  FD11 \counta_Z[0]  (
	.Q0(counta[0]),
	.D0(un6_counta[2]),
	.CLK(clk1_c)
);
// @2:67
  FD11 \count0_Z[3]  (
	.Q0(count0[3]),
	.D0(count0_n3),
	.CLK(carry)
);
// @2:91
  FD11 \count1_Z[0]  (
	.Q0(count1[0]),
	.D0(count1_e0),
	.CLK(carry)
);
// @2:67
  FD11 \count0_Z[1]  (
	.Q0(count0[1]),
	.D0(count0_n1),
	.CLK(carry)
);
// @2:67
  FD11 \count0_Z[2]  (
	.Q0(count0[2]),
	.D0(count0_n2),
	.CLK(carry)
);
// @2:48
  FD11 \count_Z[0]  (
	.Q0(count[0]),
	.D0(count_i[0]),
	.CLK(clk_c)
);
// @2:48
  FD11 \count_Z[1]  (
	.Q0(count[1]),
	.D0(count_n1),
	.CLK(clk_c)
);
// @2:48
  FD11 \count_Z[2]  (
	.Q0(count[2]),
	.D0(count_n2),
	.CLK(clk_c)
);
// @2:67
  FD11 \count0_Z[0]  (
	.Q0(count0[0]),
	.D0(count0_n0),
	.CLK(carry)
);
// @2:104
  FD11 load_Z (
	.Q0(load),
	.D0(\p4.un22_count0 ),
	.CLK(carry_i)
);
// @2:56
  FD11 carry_Z (
	.Q0(carry),
	.D0(\p11.un10_count ),
	.CLK(clk_c)
);
// @2:150
  XOR2 I_91 (
	.Z0(un6_counta[2]),
	.A0(counta[0]),
	.A1(VCC)
);
// @2:150
  AND2 I_92 (
	.Z0(N_123),
	.A0(counta[0]),
	.A1(VCC)
);
// @2:150
  XOR2 I_93 (
	.Z0(un6_counta[1]),
	.A0(counta[1]),
	.A1(N_123)
);
//@2:150
  assign VCC = 1'b1;
// @2:150
  IB11 clk_Z (
	.Z0(clk_c),
	.XI0(clk)
);
// @2:150
  IB11 clk1_Z (
	.Z0(clk1_c),
	.XI0(clk1)
);
// @2:150
  OB11 R1_Z (
	.XO0(R1),
	.A0(state_c[1])
);
// @2:150
  OB11 R2_Z (
	.XO0(R2),
	.A0(state_c_i[1])
);
// @2:150
  OB11 Y1_Z (
	.XO0(Y1),
	.A0(\p6.light10_i )
);
// @2:150
  OB11 Y2_Z (
	.XO0(Y2),
	.A0(\p6.light12_i )
);
// @2:150
  OB11 G1_Z (
	.XO0(G1),
	.A0(\p6.light9_i )
);
// @2:150
  OB11 G2_Z (
	.XO0(G2),
	.A0(\p6.light11_i )
);
// @2:150
  OB11 \segout_Z[0]  (
	.XO0(segout[0]),
	.A0(VCC)
);
// @2:150
  OB11 \segout_Z[1]  (
	.XO0(segout[1]),
	.A0(num_c[1])
);
// @2:150
  OB11 \segout_Z[2]  (
	.XO0(segout[2]),
	.A0(num_c[2])
);
// @2:150
  OB11 \segout_Z[3]  (
	.XO0(segout[3]),
	.A0(N_155_i)
);
// @2:150
  OB11 \segout_Z[4]  (
	.XO0(segout[4]),
	.A0(N_148_i)
);
// @2:150
  OB11 \segout_Z[5]  (
	.XO0(segout[5]),
	.A0(N_150_i)
);
// @2:150
  OB11 \segout_Z[6]  (
	.XO0(segout[6]),
	.A0(N_145_i)
);
// @2:150
  OB11 \segout_Z[7]  (
	.XO0(segout[7]),
	.A0(N_143_i)
);
// @2:150
  OB11 \selout_Z[0]  (
	.XO0(selout[0]),
	.A0(un1_sel_i)
);
// @2:150
  OB11 \selout_Z[1]  (
	.XO0(selout[1]),
	.A0(un3_sel_i)
);
// @2:150
  OB11 \selout_Z[2]  (
	.XO0(selout[2]),
	.A0(un9_sel_i)
);
// @2:150
  OB11 \selout_Z[3]  (
	.XO0(selout[3]),
	.A0(un1_counta_i)
);
// @2:150
  INV \p3.N_38_i  (
	.ZN0(N_38_i),
	.A0(N_38)
);
// @2:150
  INV \p3.un2_count1_i_Z  (
	.ZN0(\p3.un2_count1_i ),
	.A0(\p3.un2_count1 )
);
// @2:150
  INV \p2.un2_count0_i_Z  (
	.ZN0(\p2.un2_count0_i ),
	.A0(\p2.un2_count0 )
);
// @2:150
  INV N_141_i_Z (
	.ZN0(N_141_i),
	.A0(N_141)
);
// @2:150
  INV N_96_i_Z (
	.ZN0(N_96_i),
	.A0(N_96)
);
// @2:150
  INV N_98_i_0_i_Z (
	.ZN0(N_98_i_0_i),
	.A0(N_98_i_0)
);
// @2:150
  INV carry_i_Z (
	.ZN0(carry_i),
	.A0(carry)
);
// @2:150
  INV \count_i_Z[0]  (
	.ZN0(count_i[0]),
	.A0(count[0])
);
// @2:150
  INV N_148_i_Z (
	.ZN0(N_148_i),
	.A0(N_148)
);
// @2:150
  INV N_155_i_Z (
	.ZN0(N_155_i),
	.A0(N_155)
);
// @2:150
  INV \p6.light11_i_Z  (
	.ZN0(\p6.light11_i ),
	.A0(\p6.light11 )
);
// @2:150
  INV \p6.light9_i_Z  (
	.ZN0(\p6.light9_i ),
	.A0(\p6.light9 )
);
// @2:150
  INV \p6.light12_i_Z  (
	.ZN0(\p6.light12_i ),
	.A0(\p6.light12 )
);
// @2:150
  INV \p6.light10_i_Z  (
	.ZN0(\p6.light10_i ),
	.A0(\p6.light10 )
);
// @2:150
  INV \state_c_i_Z[1]  (
	.ZN0(state_c_i[1]),
	.A0(state_c[1])
);
// @2:150
  INV \state_i_Z[0]  (
	.ZN0(state_i[0]),
	.A0(state[0])
);
// @2:150
  INV \counta_i_Z[0]  (
	.ZN0(counta_i[0]),
	.A0(counta[0])
);
// @2:150
  INV \counta_i_Z[1]  (
	.ZN0(counta_i[1]),
	.A0(counta[1])
);
// @2:150
  INV load_i_Z (
	.ZN0(load_i),
	.A0(load)
);