trafic.log

CPLD lattice1032 VHDL实现交通灯控制！

ispEXPERT Compiler Release 0.16.51, May 20 2002 13:06:40

Copyright (C) 1994-2000 by Lattice Semiconductor Corporation.
All Rights Reserved.


Design Process Management 

Renaming existing log file to trafic.lo-
Renaming existing rpt file to trafic.rp-

Preprocessing design 'trafic'...

Processing design 'trafic'...


Logical LAF Reading and Translation 
  
Reading file 'd:\test\pt1032e\trafic\trafic.laf'... 
32583 WARNING: Pin 'A(0)' is in external pin file but not in design; pin
      'A(0)' is ignored 
32583 WARNING: Pin 'A(1)' is in external pin file but not in design; pin
      'A(1)' is ignored 
32583 WARNING: Pin 'A(2)' is in external pin file but not in design; pin
      'A(2)' is ignored 
32583 WARNING: Pin 'A(3)' is in external pin file but not in design; pin
      'A(3)' is ignored 
32583 WARNING: Pin 'B(0)' is in external pin file but not in design; pin
      'B(0)' is ignored 
32583 WARNING: Pin 'B(1)' is in external pin file but not in design; pin
      'B(1)' is ignored 
32583 WARNING: Pin 'B(2)' is in external pin file but not in design; pin
      'B(2)' is ignored 
32583 WARNING: Pin 'B(3)' is in external pin file but not in design; pin
      'B(3)' is ignored 
  
Checking design rules... 
Selected part is 'ispLSI1032E-70LJ84' 
32504 WARNING: Attribute 'Y1_AS_RESET ON' is not valid for part 
      'ispLSI1032E-70LJ84'; attribute 'Y1_AS_RESET ON' is ignored 
32513 WARNING: Net 'GND' is floating 
  
Reading hardmacro 'C:\ispTOOLS\ispcomp\macro\ld11'... 
  
Writing output files... 
  
Logical LAF reading and translation completed successfully 


Synthesis and Partitioning 
  
Reading design 'trafic'... 
  
Optimizing logic... 
  
Trying to move PT reset signal to global reset pin... 
      PT reset signal cannot be moved to global reset pin because there 
      exists no PT reset signal 
      In order to move PT reset signal to global reset pin, the 
      following conditions need to be satisfied: 
      1. There exists at least one pin which drives all register's reset
      signals 
      2. This pin is unlocked 
      3. This pin does not drive any data signals 
      4. This pin can be disjointly decomposed with other pins, if any, 
      which drive reset signals 
  
Partitioning logic into 16-input, 16-input with DIs, functions to 
      minimize delay... 
  
Extracting LXOR2 gates to minimize delay... 
  
Packing functions into GLBs using 16 inputs and 4 outputs per GLB to 
      minimize delay... 
34545 WARNING: Net 'STATE_C[1]' drives IOCs locked to different 
      megacells or different tracks; input logic is duplicated for IOC 
      'R2', new input net is 'DEF_1233' 
Constant VCC drives pin 'SEGOUT(0)' 
  
Synthesis and partitioning statistics: 
  
Number of Macrocells is 36 
Number of GLBs is 10 
Number of product terms is 103 
Maximum number of GLB levels is 3 
Average number of inputs per GLB is 7.3 
Average number of outputs per GLB is 3.6 
Average number of product terms per GLB is 10.3 
  
Synthesis and partitioning completed successfully 


Physical LAF Reading and Translation

Reading design 'trafic'...

Writing output files...

Physical LAF reading and translation completed successfully


Placement and Routing

Reading design 'trafic'...

Routing


Writing output files...

Placement and routing completed successfully


Technology Remapping 
  
Reading design 'trafic'... 
  
Remapping... 
  
Writing output files... 
  
Writing output lco files... 
  
Technology remapping completed successfully 


Physical LAF Reading and Translation

Reading design 'trafic'...

Writing output files...

Physical LAF reading and translation completed successfully


Fusemap Generation

Reading design 'trafic'...

Writing output files...

Fusemap generation completed successfully


Simulation LAF Netlist Generation

Reading design 'trafic'...

Writing output files...


Information: Global reset (XRESET) is generated to reset all registers



Simulation LAF netlist generation completed successfully


Timing Analyzer 
Reading design trafic .... 

43121 WARNING: Design has combinational cycles

Evaluating maximum operating frequency...
Evaluating setup and hold times...
43006 WARNING: No chip input pins drive data input and clock input of any register

Calculating  Tpd Path delays ...

..................

              
     
Timing analyzer completed successfully 



Lattice Verilog netlist writer
Copyright (c) 1993 - 2000 by Lattice Semiconductor Corporation.
All Rights Reserved.

writing verilog netlist ...

Verilog netlist writer completed successfully.



Lattice VHDL netlist writer
Copyright (c) 1993 - 2000 by Lattice Semiconductor Corporation.
All Rights Reserved.

writing vhdl file ...

MSG: Cross reference file [trafic.vxf] is created
       Invalid VHDL identifiers are mapped to new unique names.
       You can use -ext_id option to use extended identifiers if your
       target system supports extended VHDL identifiers.

47502 Warning: Port name [SELOUT(3)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P1].
47502 Warning: Port name [SELOUT(2)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P2].
47502 Warning: Port name [SELOUT(1)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P3].
47502 Warning: Port name [SELOUT(0)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P4].
47502 Warning: Port name [SEGOUT(7)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P5].
47502 Warning: Port name [SEGOUT(6)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P6].
47502 Warning: Port name [SEGOUT(5)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P7].
47502 Warning: Port name [SEGOUT(4)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P8].
47502 Warning: Port name [SEGOUT(3)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P9].
47502 Warning: Port name [SEGOUT(2)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P10].
47502 Warning: Port name [SEGOUT(1)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P11].
47502 Warning: Port name [SEGOUT(0)] is an invalid VHDL identifier.
         It is renamed to [UNIQPIN_P12].

Please use file [trafic.vxf] for cross referencing original and new VHDL names

VHDL netlist writer completed successfully.


Design process management completed successfully