📄 map.mrp
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Release 4.2.03i - Map E.38Xilinx Mapping Report File for Design 'COP2000'Design Information------------------Command Line : map -p xcv200-6-pq240 -o map.ncd cop2000.ngd cop2000.pcf Target Device : xv200Target Package : pq240Target Speed : -6Mapper Version : virtex -- $Revision: 1.58 $Mapped Date : Wed Dec 15 20:47:01 2004Design Summary-------------- Number of errors: 0 Number of warnings: 1 Number of Slices: 357 out of 2,352 15% Number of Slices containing unrelated logic: 0 out of 357 0% Number of Slice Flip Flops: 174 out of 4,704 3% Total Number 4 input LUTs: 557 out of 4,704 11% Number used as LUTs: 548 Number used as a route-thru: 9 Number of bonded IOBs: 74 out of 166 44% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 5,031Additional JTAG gate count for IOBs: 3,600Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:MapLib:135 - Clock buffer is designated to drive clock loads. BUFGP
symbol "C5636" (output signal=clk_BUFGPed) has a mix of clock and non-clock
loads.Section 3 - Informational-------------------------INFO:MapLib:62 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary--------------------------------- 21 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKVCC C5659GND C5660GND C5661GND C5662GND C5663GND C5664GND C5665GND C5666GND C5667GND C5668GND C5669GND C5670GND C5671GND C5672GND C5673GND C5674GND C5675GND C5676GND C5677GND C5678GND C5679To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || PRST | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PXRD | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || PXWR | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || i_req | IOB | INPUT | LVTTL | | | | | || keyin<0> | IOB | INPUT | LVTTL | | | | | || keyin<10> | IOB | INPUT | LVTTL | | | | | || keyin<11> | IOB | INPUT | LVTTL | | | | | || keyin<12> | IOB | INPUT | LVTTL | | | | | || keyin<13> | IOB | INPUT | LVTTL | | | | | || keyin<14> | IOB | INPUT | LVTTL | | | | | || keyin<15> | IOB | INPUT | LVTTL | | | | | || keyin<1> | IOB | INPUT | LVTTL | | | | | || keyin<2> | IOB | INPUT | LVTTL | | | | | || keyin<3> | IOB | INPUT | LVTTL | | | | | || keyin<4> | IOB | INPUT | LVTTL | | | | | || keyin<5> | IOB | INPUT | LVTTL | | | | | || keyin<6> | IOB | INPUT | LVTTL | | | | | || keyin<7> | IOB | INPUT | LVTTL | | | | | || keyin<8> | IOB | INPUT | LVTTL | | | | | || keyin<9> | IOB | INPUT | LVTTL | | | | | || mem_a<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_a<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_bh | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_bl | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_cs | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_d<0> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<10> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<11> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<12> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<13> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<14> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<15> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<1> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<2> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<3> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<4> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<5> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<6> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<7> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<8> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_d<9> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || mem_rd | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_wr | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || portout<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || rst | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.⌨️ 快捷键说明
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