cop2000.twr

cop2000试验仪的模拟器

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Release 4.2.03i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce cop2000.ncd cop2000.pcf -e 3 -o cop2000.twr -xml cop2000.twx

Design file:              cop2000.ncd
Physical constraint file: cop2000.pcf
Device,speed:             xcv200,-6 (FINAL 1.116 2001-12-19)
Report level:             error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis

 1323425 items analyzed, 0 timing errors detected.
 Minimum period is  30.509ns.
 Maximum delay is  35.106ns.
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================================================================================
Timing constraint: Default net enumeration

 775 items analyzed, 0 timing errors detected.
 Maximum net delay is   6.837ns.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
keyin<0>       |    8.341(R)|    0.000(R)|
keyin<10>      |    9.501(R)|    0.000(R)|
keyin<11>      |    9.107(R)|    0.000(R)|
keyin<12>      |    9.208(R)|    0.000(R)|
keyin<13>      |   11.292(R)|    0.000(R)|
keyin<14>      |   11.557(R)|    0.000(R)|
keyin<15>      |   11.695(R)|    0.000(R)|
keyin<1>       |    9.416(R)|    0.000(R)|
keyin<2>       |    9.485(R)|    0.000(R)|
keyin<3>       |    8.106(R)|    0.000(R)|
keyin<4>       |    9.897(R)|    0.000(R)|
keyin<5>       |    8.578(R)|    0.000(R)|
keyin<6>       |    9.647(R)|    0.000(R)|
keyin<7>       |    8.457(R)|    0.000(R)|
keyin<8>       |   10.657(R)|    0.000(R)|
keyin<9>       |   10.814(R)|    0.000(R)|
mem_d<0>       |   11.297(R)|    0.000(R)|
mem_d<10>      |    4.938(R)|    0.000(R)|
mem_d<11>      |    4.844(R)|    0.000(R)|
mem_d<12>      |    4.155(R)|    0.000(R)|
mem_d<13>      |    4.971(R)|    0.000(R)|
mem_d<14>      |    4.486(R)|    0.000(R)|
mem_d<15>      |    5.010(R)|    0.000(R)|
mem_d<1>       |    9.504(R)|    0.000(R)|
mem_d<2>       |   10.852(R)|    0.000(R)|
mem_d<3>       |    9.516(R)|    0.000(R)|
mem_d<4>       |    9.492(R)|    0.000(R)|
mem_d<5>       |   10.280(R)|    0.000(R)|
mem_d<6>       |   11.311(R)|    0.000(R)|
mem_d<7>       |   10.162(R)|    0.000(R)|
mem_d<8>       |    4.493(R)|    0.000(R)|
mem_d<9>       |    4.413(R)|    0.000(R)|
---------------+------------+------------+

Clock clk to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
PXRD           |   16.075(R)|
PXWR           |   16.605(R)|
mem_a<0>       |   24.713(R)|
mem_a<10>      |   23.590(R)|
mem_a<11>      |   24.218(R)|
mem_a<12>      |   23.424(R)|
mem_a<13>      |   23.858(R)|
mem_a<14>      |   22.874(R)|
mem_a<15>      |   24.337(R)|
mem_a<1>       |   24.162(R)|
mem_a<2>       |   24.487(R)|
mem_a<3>       |   24.370(R)|
mem_a<4>       |   24.226(R)|
mem_a<5>       |   25.133(R)|
mem_a<6>       |   24.210(R)|
mem_a<7>       |   24.776(R)|
mem_a<8>       |   24.764(R)|
mem_a<9>       |   23.892(R)|
mem_d<0>       |   33.094(R)|
mem_d<10>      |   34.575(R)|
mem_d<11>      |   34.407(R)|
mem_d<12>      |   35.612(R)|
mem_d<13>      |   35.648(R)|
mem_d<14>      |   35.863(R)|
mem_d<15>      |   36.856(R)|
mem_d<1>       |   35.126(R)|
mem_d<2>       |   33.588(R)|
mem_d<3>       |   35.316(R)|
mem_d<4>       |   34.111(R)|
mem_d<5>       |   34.015(R)|
mem_d<6>       |   34.545(R)|
mem_d<7>       |   35.324(R)|
mem_d<8>       |   34.019(R)|
mem_d<9>       |   34.700(R)|
mem_rd         |   21.927(R)|
mem_wr         |   18.656(X)|
portout<0>     |   10.495(R)|
portout<10>    |    9.410(R)|
portout<11>    |    9.388(R)|
portout<12>    |   10.008(R)|
portout<13>    |    9.810(R)|
portout<14>    |    9.819(R)|
portout<15>    |   10.060(R)|
portout<1>     |   10.194(R)|
portout<2>     |    9.995(R)|
portout<3>     |   10.621(R)|
portout<4>     |    9.740(R)|
portout<5>     |    9.786(R)|
portout<6>     |    9.250(R)|
portout<7>     |    9.264(R)|
portout<8>     |    9.589(R)|
portout<9>     |    9.928(R)|
---------------+------------+

Clock i_req to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
mem_d<0>       |   18.695(R)|
mem_d<10>      |   20.298(R)|
mem_d<11>      |   20.522(R)|
mem_d<12>      |   20.637(R)|
mem_d<13>      |   20.912(R)|
mem_d<14>      |   20.838(R)|
mem_d<15>      |   20.304(R)|
mem_d<1>       |   18.606(R)|
mem_d<2>       |   19.844(R)|
mem_d<3>       |   18.510(R)|
mem_d<4>       |   19.330(R)|
mem_d<5>       |   18.995(R)|
mem_d<6>       |   19.118(R)|
mem_d<7>       |   19.541(R)|
mem_d<8>       |   19.836(R)|
mem_d<9>       |   20.304(R)|
mem_rd         |   16.182(R)|
---------------+------------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   30.509|         |         |         |
i_req          |   14.305|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
keyin<0>       |mem_d<0>       |   14.330|
keyin<10>      |mem_d<10>      |   14.957|
keyin<11>      |mem_d<11>      |   14.816|
keyin<12>      |mem_d<12>      |   15.407|
keyin<13>      |mem_d<13>      |   17.242|
keyin<14>      |mem_d<14>      |   17.744|
keyin<15>      |mem_d<15>      |   17.357|
keyin<1>       |mem_d<1>       |   14.816|
keyin<2>       |mem_d<2>       |   15.385|
keyin<3>       |mem_d<3>       |   14.260|
keyin<4>       |mem_d<4>       |   16.422|
keyin<5>       |mem_d<5>       |   14.192|
keyin<6>       |mem_d<6>       |   14.606|
keyin<7>       |mem_d<7>       |   14.565|
keyin<8>       |mem_d<8>       |   15.766|
keyin<9>       |mem_d<9>       |   16.103|
rst            |PRST           |    8.568|
---------------+---------------+---------+

WARNING:Timing:2554 - Clock nets using non-dedicated resources were found in
   this design. Clock skew on these resources will not be automatically
   addressed during path analysis. To create a timing report that analyzes
   clock skew for these paths, run trce with the '-skew' option.

   The following clock nets use non-dedicated resources:
      N_i_req  


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1323425 paths, 775 nets, and 2448 connections (100.0% coverage)

Design statistics:
   Minimum period:  30.509ns (Maximum frequency:  32.777MHz)
   Maximum combinational path delay:  35.106ns
   Maximum net delay:   6.837ns


Analysis completed Wed Dec 15 20:47:17 2004
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