cop2000.par

cop2000试验仪的模拟器

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Wed Dec 15 20:47:07 2004

par -w -ol 2 map.ncd cop2000.ncd cop2000.pcf


Constraints file: cop2000.pcf

Loading design for application par from file map.ncd.
   "COP2000" is an NCD, version 2.37, device xcv200, package pq240, speed -6
Loading device for application par from file 'v200.nph' in environment
C:/xilinx.
Device speed data version:  FINAL 1.116 2001-12-19.


Resolved that IOB <portout<10>> must be placed at site P232.
Resolved that IOB <portout<11>> must be placed at site P231.
Resolved that IOB <portout<12>> must be placed at site P230.
Resolved that IOB <portout<13>> must be placed at site P229.
Resolved that IOB <portout<14>> must be placed at site P228.
Resolved that IOB <portout<15>> must be placed at site P224.
Resolved that IOB <i_req> must be placed at site P111.
Resolved that IOB <PRST> must be placed at site P142.
Resolved that IOB <PXRD> must be placed at site P141.
Resolved that IOB <PXWR> must be placed at site P140.
Resolved that IOB <mem_a<0>> must be placed at site P153.
Resolved that IOB <mem_a<1>> must be placed at site P154.
Resolved that IOB <mem_a<2>> must be placed at site P155.
Resolved that IOB <mem_a<3>> must be placed at site P156.
Resolved that IOB <mem_a<4>> must be placed at site P157.
Resolved that IOB <mem_a<5>> must be placed at site P173.
Resolved that IOB <mem_a<6>> must be placed at site P174.
Resolved that IOB <mem_a<7>> must be placed at site P175.
Resolved that IOB <mem_a<8>> must be placed at site P176.
Resolved that IOB <mem_a<9>> must be placed at site P186.
Resolved that IOB <mem_d<0>> must be placed at site P160.
Resolved that IOB <mem_d<1>> must be placed at site P161.
Resolved that IOB <mem_d<2>> must be placed at site P162.
Resolved that IOB <mem_d<3>> must be placed at site P163.
Resolved that IOB <mem_d<4>> must be placed at site P167.
Resolved that IOB <mem_d<5>> must be placed at site P168.
Resolved that IOB <mem_d<6>> must be placed at site P169.
Resolved that IOB <mem_d<7>> must be placed at site P170.
Resolved that IOB <mem_d<8>> must be placed at site P202.
Resolved that IOB <mem_d<9>> must be placed at site P201.
Resolved that IOB <portout<0>> must be placed at site P223.
Resolved that IOB <portout<1>> must be placed at site P222.
Resolved that IOB <portout<2>> must be placed at site P221.
Resolved that IOB <portout<3>> must be placed at site P220.
Resolved that IOB <portout<4>> must be placed at site P218.
Resolved that IOB <portout<5>> must be placed at site P217.
Resolved that IOB <portout<6>> must be placed at site P216.
Resolved that IOB <portout<7>> must be placed at site P215.
Resolved that IOB <portout<8>> must be placed at site P235.
Resolved that IOB <portout<9>> must be placed at site P234.
Resolved that IOB <keyin<10>> must be placed at site P85.
Resolved that IOB <keyin<11>> must be placed at site P84.
Resolved that IOB <keyin<12>> must be placed at site P82.
Resolved that IOB <keyin<13>> must be placed at site P81.
Resolved that IOB <keyin<14>> must be placed at site P80.
Resolved that IOB <keyin<15>> must be placed at site P79.
Resolved that IOB <mem_bh> must be placed at site P189.
Resolved that IOB <mem_bl> must be placed at site P191.
Resolved that IOB <mem_cs> must be placed at site P159.
Resolved that IOB <mem_rd> must be placed at site P188.
Resolved that IOB <mem_wr> must be placed at site P171.
Resolved that GCLKIOB <clk> must be placed at site P92.
Resolved that IOB <keyin<0>> must be placed at site P103.
Resolved that IOB <keyin<1>> must be placed at site P102.
Resolved that IOB <keyin<2>> must be placed at site P101.
Resolved that IOB <keyin<3>> must be placed at site P100.
Resolved that IOB <keyin<4>> must be placed at site P97.
Resolved that IOB <mem_a<10>> must be placed at site P185.
Resolved that IOB <keyin<5>> must be placed at site P96.
Resolved that IOB <mem_a<11>> must be placed at site P208.
Resolved that IOB <keyin<6>> must be placed at site P95.
Resolved that IOB <mem_a<12>> must be placed at site P207.
Resolved that IOB <keyin<7>> must be placed at site P94.
Resolved that IOB <mem_a<13>> must be placed at site P206.
Resolved that IOB <keyin<8>> must be placed at site P87.
Resolved that IOB <mem_a<14>> must be placed at site P205.
Resolved that IOB <keyin<9>> must be placed at site P86.
Resolved that IOB <mem_a<15>> must be placed at site P187.
Resolved that IOB <rst> must be placed at site P33.
Resolved that IOB <mem_d<10>> must be placed at site P200.
Resolved that IOB <mem_d<11>> must be placed at site P199.
Resolved that IOB <mem_d<12>> must be placed at site P195.
Resolved that IOB <mem_d<13>> must be placed at site P194.
Resolved that IOB <mem_d<14>> must be placed at site P193.
Resolved that IOB <mem_d<15>> must be placed at site P192.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            74 out of 166    44%
      Number of LOCed External IOBs   74 out of 74    100%

   Number of SLICEs                  357 out of 2352   15%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (default)

Starting the placer. REAL time: 2 secs 
Placement pass 1 ....
Placer score = 89860
Placement pass 2 ........
Placer score = 82535
Optimizing ... 
Placer score = 70180
All IOBs have been constrained to specific sites.
Placer completed in real time: 3 secs 

Dumping design to file cop2000.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 

0 connection(s) routed; 2448 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 3 secs 
Starting iterative routing. 
Routing active signals.
......
End of iteration 1 
2448 successful; 0 unrouted; (0) REAL time: 5 secs 
Constraints are met. 
Total REAL time: 5 secs 
Total CPU  time: 4 secs 
End of route.  2448 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 289


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.973 ns
   The Maximum Pin Delay is:                               6.837 ns
   The Average Connection Delay on the 10 Worst Nets is:   4.610 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
         590         886         493         220         259           0

Dumping design to file cop2000.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 4 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.