testcop2.par

cop2000试验仪的模拟器

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Wed Dec 15 14:45:36 2004

par -w -ol 2 map.ncd testcop2.ncd testcop2.pcf


Constraints file: testcop2.pcf

Loading design for application par from file map.ncd.
   "TESTCOP2" is an NCD, version 2.37, device xcv200, package pq240, speed -6
Loading device for application par from file 'v200.nph' in environment
C:/xilinx.
Device speed data version:  FINAL 1.116 2001-12-19.


Resolved that IOB <K5<0>> must be placed at site P208.
Resolved that IOB <K5<1>> must be placed at site P207.
Resolved that IOB <K5<2>> must be placed at site P206.
Resolved that IOB <K5<3>> must be placed at site P205.
Resolved that IOB <LED10<0>> must be placed at site P139.
Resolved that IOB <K6<0>> must be placed at site P194.
Resolved that IOB <K5<4>> must be placed at site P202.
Resolved that IOB <LED10<1>> must be placed at site P140.
Resolved that IOB <K6<1>> must be placed at site P193.
Resolved that IOB <K5<5>> must be placed at site P201.
Resolved that IOB <LED10<2>> must be placed at site P141.
Resolved that IOB <K6<2>> must be placed at site P192.
Resolved that IOB <K5<6>> must be placed at site P200.
Resolved that IOB <LED10<3>> must be placed at site P142.
Resolved that IOB <K6<3>> must be placed at site P191.
Resolved that IOB <K5<7>> must be placed at site P199.
Resolved that IOB <LED10<4>> must be placed at site P144.
Resolved that IOB <LED8<0>> must be placed at site P33.
Resolved that IOB <K6<4>> must be placed at site P189.
Resolved that IOB <LED10<5>> must be placed at site P145.
Resolved that IOB <LED8<1>> must be placed at site P34.
Resolved that IOB <K6<5>> must be placed at site P188.
Resolved that IOB <LED10<6>> must be placed at site P146.
Resolved that IOB <LED8<2>> must be placed at site P35.
Resolved that IOB <K6<6>> must be placed at site P187.
Resolved that IOB <LED10<7>> must be placed at site P147.
Resolved that IOB <LED8<3>> must be placed at site P36.
Resolved that IOB <K6<7>> must be placed at site P186.
Resolved that IOB <LED9<0>> must be placed at site P46.
Resolved that IOB <LED8<4>> must be placed at site P38.
Resolved that IOB <LED9<1>> must be placed at site P47.
Resolved that IOB <LED8<5>> must be placed at site P39.
Resolved that IOB <LED9<2>> must be placed at site P48.
Resolved that IOB <LED8<6>> must be placed at site P40.
Resolved that IOB <LED9<3>> must be placed at site P49.
Resolved that IOB <LED8<7>> must be placed at site P41.
Resolved that IOB <LED9<4>> must be placed at site P52.
Resolved that IOB <LED9<5>> must be placed at site P53.
Resolved that IOB <LED9<6>> must be placed at site P54.
Resolved that IOB <LED9<7>> must be placed at site P55.


Device utilization summary:

   Number of External IOBs            40 out of 166    24%
      Number of LOCed External IOBs   40 out of 40    100%





Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (default)

Starting the placer. REAL time: 0 secs 
Placement pass 1 .
Placer score = 14700
Placement pass 2 .
Placer score = 14700
Optimizing ... 
Placer score = 14700
All IOBs have been constrained to specific sites.
Placer completed in real time: 0 secs 

Dumping design to file testcop2.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 

0 connection(s) routed; 24 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 0 secs 
Starting iterative routing. 
Routing active signals.
....
End of iteration 1 
24 successful; 0 unrouted; (0) REAL time: 0 secs 
Constraints are met. 
Total REAL time: 0 secs 
Total CPU  time: 1 secs 
End of route.  24 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 597


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        4.889 ns
   The Maximum Pin Delay is:                               5.759 ns
   The Average Connection Delay on the 10 Worst Nets is:   5.430 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
           0           0           0           2          22           0

Dumping design to file testcop2.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.