testcop2.twr

cop2000试验仪的模拟器

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Release 4.2.03i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce testcop2.ncd testcop2.pcf -e 3 -o testcop2.twr -xml testcop2.twx

Design file:              testcop2.ncd
Physical constraint file: testcop2.pcf
Device,speed:             xcv200,-6 (FINAL 1.116 2001-12-19)
Report level:             error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis

 24 items analyzed, 0 timing errors detected.
 Maximum delay is  11.314ns.
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================================================================================
Timing constraint: Default net enumeration

 16 items analyzed, 0 timing errors detected.
 Maximum net delay is   5.759ns.
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All constraints were met.


Data Sheet report:
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All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
K5<0>          |LED10<0>       |    9.886|
K5<0>          |LED8<0>        |   10.777|
K5<1>          |LED10<1>       |   10.274|
K5<1>          |LED8<1>        |   11.014|
K5<2>          |LED10<2>       |   10.216|
K5<2>          |LED8<2>        |   10.887|
K5<3>          |LED10<3>       |   10.386|
K5<3>          |LED8<3>        |   10.420|
K5<4>          |LED10<4>       |    9.797|
K5<4>          |LED8<4>        |   11.173|
K5<5>          |LED10<5>       |    9.684|
K5<5>          |LED8<5>        |   10.704|
K5<6>          |LED10<6>       |    9.950|
K5<6>          |LED8<6>        |   11.164|
K5<7>          |LED10<7>       |   10.110|
K5<7>          |LED8<7>        |   10.999|
K6<0>          |LED9<0>        |   10.428|
K6<1>          |LED9<1>        |    9.510|
K6<2>          |LED9<2>        |   11.207|
K6<3>          |LED9<3>        |    9.190|
K6<4>          |LED9<4>        |   10.653|
K6<5>          |LED9<5>        |   10.731|
K6<6>          |LED9<6>        |   11.314|
K6<7>          |LED9<7>        |   10.193|
---------------+---------------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 24 paths, 16 nets, and 24 connections (100.0% coverage)

Design statistics:
   Maximum combinational path delay:  11.314ns
   Maximum net delay:   5.759ns


Analysis completed Wed Dec 15 14:45:39 2004
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