map.mrp

来自「cop2000试验仪的模拟器」· MRP 代码 · 共 224 行 · 第 1/2 页

Release 4.2.03i - Map E.38
Xilinx Mapping Report File for Design 'TESTCOP1'

Design Information
------------------
Command Line   : map -p xcv200-6-pq240 -o map.ncd testcop1.ngd testcop1.pcf 
Target Device  : xv200
Target Package : pq240
Target Speed   : -6
Mapper Version : virtex -- $Revision: 1.58 $
Mapped Date    : Tue Sep 14 12:40:15 2004

Design Summary
--------------
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                  0 out of  2,352    0%
   Number of Slices containing
      unrelated logic:                0 out of      0    0%
   Number of 4 input LUTs:            0 out of  4,704    0%
   Number of bonded IOBs:           142 out of    166   85%
Total equivalent gate count for design:  48
Additional JTAG gate count for IOBs:  6,816

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:62 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| A17                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AH<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| AL<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| BH                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| BL                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| CS                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| DH<0>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<1>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<2>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<3>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<4>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<5>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<6>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DH<7>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<0>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<1>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<2>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<3>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<4>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<5>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<6>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| DL<7>                              | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       |
| K0<0>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<1>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<2>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<3>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<4>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<5>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<6>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K0<7>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K1<0>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K1<1>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| K1<2>                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |