📄 testcop1.twr
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Release 4.2.03i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
trce testcop1.ncd testcop1.pcf -e 3 -o testcop1.twr -xml testcop1.twx
Design file: testcop1.ncd
Physical constraint file: testcop1.pcf
Device,speed: xcv200,-6 (FINAL 1.116 2001-12-19)
Report level: error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.
================================================================================
Timing constraint: Default period analysis
118 items analyzed, 0 timing errors detected.
Maximum delay is 11.966ns.
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================================================================================
Timing constraint: Default net enumeration
56 items analyzed, 0 timing errors detected.
Maximum net delay is 6.395ns.
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All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
DH<0> |LED7<0> | 9.376|
DH<1> |LED7<1> | 9.698|
DH<2> |LED7<2> | 7.006|
DH<3> |LED7<3> | 7.466|
DH<4> |LED7<4> | 7.645|
DH<5> |LED7<5> | 7.574|
DH<6> |LED7<6> | 10.191|
DH<7> |LED7<7> | 9.429|
DL<0> |LED6<0> | 7.704|
DL<1> |LED6<1> | 7.594|
DL<2> |LED6<2> | 8.513|
DL<3> |LED6<3> | 8.859|
DL<4> |LED6<4> | 9.014|
DL<5> |LED6<5> | 9.006|
DL<6> |LED6<6> | 10.266|
DL<7> |LED6<7> | 10.204|
K0<0> |DL<0> | 9.791|
K0<0> |LED0<0> | 10.391|
K0<0> |LED5<0> | 8.095|
K0<1> |DL<1> | 10.020|
K0<1> |LED0<1> | 10.703|
K0<1> |LED5<1> | 7.726|
K0<2> |DL<2> | 10.271|
K0<2> |LED0<2> | 9.828|
K0<2> |LED5<2> | 7.790|
K0<3> |DL<3> | 9.973|
K0<3> |LED0<3> | 10.237|
K0<3> |LED5<3> | 7.741|
K0<4> |DL<4> | 10.287|
K0<4> |LED0<4> | 9.735|
K0<4> |LED5<4> | 7.971|
K0<5> |DL<5> | 10.441|
K0<5> |LED0<5> | 9.947|
K0<5> |LED5<5> | 8.399|
K0<6> |DL<6> | 10.299|
K0<6> |LED0<6> | 11.155|
K0<6> |LED5<6> | 9.335|
K0<7> |DL<7> | 10.459|
K0<7> |LED0<7> | 9.590|
K0<7> |LED5<7> | 9.555|
K1<0> |DH<0> | 9.679|
K1<0> |LED1<0> | 9.948|
K1<1> |DH<1> | 10.652|
K1<1> |LED1<1> | 10.027|
K1<2> |DH<2> | 10.284|
K1<2> |LED1<2> | 10.016|
K1<3> |DH<3> | 10.034|
K1<3> |LED1<3> | 10.036|
K1<4> |DH<4> | 10.589|
K1<4> |LED1<4> | 9.491|
K1<5> |DH<5> | 10.305|
K1<5> |LED1<5> | 9.728|
K1<6> |DH<6> | 10.559|
K1<6> |LED1<6> | 9.227|
K1<7> |DH<7> | 10.889|
K1<7> |LED1<7> | 9.082|
K2<0> |AL<0> | 10.028|
K2<0> |LED2<0> | 11.019|
K2<1> |AL<1> | 10.122|
K2<1> |LED2<1> | 10.551|
K2<2> |AL<2> | 10.075|
K2<2> |LED2<2> | 10.363|
K2<3> |AL<3> | 9.440|
K2<3> |LED2<3> | 9.559|
K2<4> |AL<4> | 10.215|
K2<4> |LED2<4> | 9.401|
K2<5> |AL<5> | 11.294|
K2<5> |LED2<5> | 9.100|
K2<6> |AL<6> | 11.950|
K2<6> |LED2<6> | 9.122|
K2<7> |AL<7> | 11.933|
K2<7> |LED2<7> | 9.189|
K3<0> |AH<0> | 10.974|
K3<0> |LED3<0> | 7.808|
K3<1> |AH<1> | 9.790|
K3<1> |LED3<1> | 7.554|
K3<2> |AH<2> | 10.590|
K3<2> |LED3<2> | 7.828|
K3<3> |AH<3> | 9.154|
K3<3> |LED3<3> | 7.791|
K3<4> |AH<4> | 10.059|
K3<4> |LED3<4> | 7.605|
K3<5> |AH<5> | 10.771|
K3<5> |LED3<5> | 8.107|
K3<6> |AH<6> | 10.726|
K3<6> |LED3<6> | 8.122|
K3<7> |AH<7> | 10.941|
K3<7> |LED3<7> | 8.122|
K4<0> |LED4<0> | 7.376|
K4<1> |A17 | 9.836|
K4<1> |LED4<1> | 7.351|
K4<2> |CS | 8.853|
K4<2> |LED4<2> | 7.400|
K4<3> |LED4<3> | 7.336|
K4<3> |WR | 9.319|
K4<4> |DH<0> | 11.208|
K4<4> |DH<1> | 11.857|
K4<4> |DH<2> | 11.885|
K4<4> |DH<3> | 11.669|
K4<4> |DH<4> | 11.761|
K4<4> |DH<5> | 11.966|
K4<4> |DH<6> | 11.087|
K4<4> |DH<7> | 10.114|
K4<4> |DL<0> | 9.373|
K4<4> |DL<1> | 10.087|
K4<4> |DL<2> | 10.162|
K4<4> |DL<3> | 10.162|
K4<4> |DL<4> | 10.162|
K4<4> |DL<5> | 10.087|
K4<4> |DL<6> | 10.087|
K4<4> |DL<7> | 10.898|
K4<4> |LED4<4> | 7.025|
K4<4> |RD | 9.794|
K4<5> |BH | 9.837|
K4<5> |LED4<5> | 7.014|
K4<6> |BL | 9.816|
K4<6> |LED4<6> | 7.399|
K4<7> |LED4<7> | 7.338|
---------------+---------------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 118 paths, 56 nets, and 118 connections (100.0% coverage)
Design statistics:
Maximum combinational path delay: 11.966ns
Maximum net delay: 6.395ns
Analysis completed Wed Dec 15 14:43:50 2004
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