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📄 map.mrp

📁 cop2000试验仪的模拟器
💻 MRP
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Release 4.2.03i - Map E.38Xilinx Mapping Report File for Design 'RS232'Design Information------------------Command Line   : map -p xcv200-6-pq240 -o map.ncd rs232.ngd rs232.pcf Target Device  : xv200Target Package : pq240Target Speed   : -6Mapper Version : virtex -- $Revision: 1.58 $Mapped Date    : Thu Dec 16 10:16:02 2004Design Summary--------------   Number of errors:      0   Number of warnings:    0   Number of Slices:                 80 out of  2,352    3%   Number of Slices containing      unrelated logic:                0 out of     80    0%   Number of Slice Flip Flops:       73 out of  4,704    1%   Number of 4 input LUTs:          110 out of  4,704    2%   Number of bonded IOBs:            35 out of    166   21%   Number of GCLKs:                   2 out of      4   50%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  1,313Additional JTAG gate count for IOBs:  1,728Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:62 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKVCC 		C1265GND 		C1266To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || PBCLK                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRI                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<0>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<1>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<2>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<3>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<4>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<5>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<6>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRSBUF<7>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTI                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<0>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<1>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<2>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<3>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<4>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<5>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<6>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PTSBUF<7>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PXMIT                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || addrport<0>                        | IOB     | INPUT     | LVTTL       |          |      |          |          |       || addrport<1>                        | IOB     | INPUT     | LVTTL       |          |      |          |          |       || dataport<0>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<1>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<2>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<3>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<4>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<5>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<6>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || dataport<7>                        | IOB     | BIDIR     | LVTTL       | 12       | SLOW |          |          |       || rst                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       || rxd                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       || txd                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || xrd                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       || xwr                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.

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