rs232.twr

cop2000试验仪的模拟器

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Release 4.2.03i - Trace E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

trce rs232.ncd rs232.pcf -e 3 -o rs232.twr -xml rs232.twx

Design file:              rs232.ncd
Physical constraint file: rs232.pcf
Device,speed:             xcv200,-6 (FINAL 1.116 2001-12-19)
Report level:             error report
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WARNING:Timing:2491 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis

 1147 items analyzed, 0 timing errors detected.
 Minimum period is   9.377ns.
 Maximum delay is  14.356ns.
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================================================================================
Timing constraint: Default net enumeration

 173 items analyzed, 0 timing errors detected.
 Maximum net delay is   6.782ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
addrport<0>    |    4.146(R)|    0.000(R)|
addrport<1>    |    4.552(R)|    0.000(R)|
dataport<0>    |    2.279(R)|    0.119(R)|
dataport<1>    |    2.087(R)|    0.055(R)|
dataport<2>    |    1.957(R)|    0.155(R)|
dataport<3>    |    2.088(R)|    0.077(R)|
dataport<4>    |    2.132(R)|    0.007(R)|
dataport<5>    |    2.507(R)|    0.000(R)|
dataport<6>    |    2.380(R)|    0.003(R)|
dataport<7>    |    2.653(R)|    0.225(R)|
xrd            |    5.247(R)|    0.000(R)|
xwr            |    5.634(R)|    0.000(R)|
---------------+------------+------------+

Clock clk to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
PBCLK          |   16.106(R)|
PTSBUF<0>      |    8.872(R)|
PTSBUF<1>      |    8.864(R)|
PTSBUF<2>      |    9.104(R)|
PTSBUF<3>      |    9.116(R)|
PTSBUF<4>      |    9.301(R)|
PTSBUF<5>      |    9.310(R)|
PTSBUF<6>      |    9.553(R)|
PTSBUF<7>      |    9.288(R)|
PXMIT          |   11.170(R)|
---------------+------------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.996|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
addrport<0>    |dataport<0>    |   10.586|
addrport<0>    |dataport<1>    |   11.331|
addrport<0>    |dataport<2>    |   10.860|
addrport<0>    |dataport<3>    |   11.428|
addrport<0>    |dataport<4>    |   10.998|
addrport<0>    |dataport<5>    |   10.686|
addrport<0>    |dataport<6>    |   11.178|
addrport<0>    |dataport<7>    |   10.011|
addrport<1>    |dataport<0>    |   10.757|
addrport<1>    |dataport<1>    |   11.369|
addrport<1>    |dataport<2>    |   10.898|
addrport<1>    |dataport<3>    |   11.466|
addrport<1>    |dataport<4>    |   11.036|
addrport<1>    |dataport<5>    |   10.917|
addrport<1>    |dataport<6>    |   11.261|
addrport<1>    |dataport<7>    |   10.735|
rst            |dataport<0>    |   13.299|
rst            |dataport<1>    |   14.044|
rst            |dataport<2>    |   13.573|
rst            |dataport<3>    |   14.141|
rst            |dataport<4>    |   13.711|
rst            |dataport<5>    |   13.399|
rst            |dataport<6>    |   13.891|
rst            |dataport<7>    |   12.724|
xrd            |dataport<0>    |   12.896|
xrd            |dataport<1>    |   13.641|
xrd            |dataport<2>    |   13.170|
xrd            |dataport<3>    |   13.738|
xrd            |dataport<4>    |   13.308|
xrd            |dataport<5>    |   12.996|
xrd            |dataport<6>    |   13.488|
xrd            |dataport<7>    |   12.321|
---------------+---------------+---------+

WARNING:Timing:2554 - Clock nets using non-dedicated resources were found in
   this design. Clock skew on these resources will not be automatically
   addressed during path analysis. To create a timing report that analyzes
   clock skew for these paths, run trce with the '-skew' option.

   The following clock nets use non-dedicated resources:
      N941_BUFGed  


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1147 paths, 173 nets, and 536 connections (100.0% coverage)

Design statistics:
   Minimum period:   9.377ns (Maximum frequency: 106.644MHz)
   Maximum combinational path delay:  14.356ns
   Maximum net delay:   6.782ns


Analysis completed Thu Dec 16 10:16:11 2004
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