rs232.par

cop2000试验仪的模拟器

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Thu Dec 16 10:16:06 2004

par -w -ol 2 map.ncd rs232.ncd rs232.pcf


Constraints file: rs232.pcf

Loading design for application par from file map.ncd.
   "RS232" is an NCD, version 2.37, device xcv200, package pq240, speed -6
Loading device for application par from file 'v200.nph' in environment
C:/xilinx.
Device speed data version:  FINAL 1.116 2001-12-19.


Resolved that IOB <dataport<7>> must be placed at site P10.
Resolved that IOB <xrd> must be placed at site P71.
Resolved that GCLKIOB <clk> must be placed at site P92.
Resolved that IOB <PRSBUF<0>> must be placed at site P46.
Resolved that IOB <PRSBUF<1>> must be placed at site P47.
Resolved that IOB <PRSBUF<2>> must be placed at site P48.
Resolved that IOB <PRSBUF<3>> must be placed at site P49.
Resolved that IOB <PRSBUF<4>> must be placed at site P52.
Resolved that IOB <xwr> must be placed at site P72.
Resolved that IOB <PRSBUF<5>> must be placed at site P53.
Resolved that IOB <PRSBUF<6>> must be placed at site P54.
Resolved that IOB <PRSBUF<7>> must be placed at site P55.
Resolved that IOB <PRI> must be placed at site P140.
Resolved that IOB <PTI> must be placed at site P139.
Resolved that IOB <addrport<0>> must be placed at site P28.
Resolved that IOB <addrport<1>> must be placed at site P27.
Resolved that IOB <PTSBUF<0>> must be placed at site P33.
Resolved that IOB <PTSBUF<1>> must be placed at site P34.
Resolved that IOB <PTSBUF<2>> must be placed at site P35.
Resolved that IOB <PTSBUF<3>> must be placed at site P36.
Resolved that IOB <PTSBUF<4>> must be placed at site P38.
Resolved that IOB <PTSBUF<5>> must be placed at site P39.
Resolved that IOB <PTSBUF<6>> must be placed at site P40.
Resolved that IOB <PBCLK> must be placed at site P141.
Resolved that IOB <PTSBUF<7>> must be placed at site P41.
Resolved that IOB <dataport<0>> must be placed at site P21.
Resolved that IOB <rxd> must be placed at site P125.
Resolved that IOB <dataport<1>> must be placed at site P20.
Resolved that IOB <dataport<2>> must be placed at site P19.
Resolved that IOB <dataport<3>> must be placed at site P18.
Resolved that IOB <dataport<4>> must be placed at site P13.
Resolved that IOB <rst> must be placed at site P70.
Resolved that IOB <dataport<5>> must be placed at site P12.
Resolved that IOB <txd> must be placed at site P124.
Resolved that IOB <PXMIT> must be placed at site P142.
Resolved that IOB <dataport<6>> must be placed at site P11.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            35 out of 166    21%
      Number of LOCed External IOBs   35 out of 35    100%

   Number of SLICEs                   80 out of 2352    3%

   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (default)

Starting the placer. REAL time: 0 secs 
Placement pass 1 ..
Placer score = 22755
Placement pass 2 ..
Placer score = 19960
Optimizing ... 
Placer score = 18300
All IOBs have been constrained to specific sites.
Placer completed in real time: 2 secs 

Dumping design to file rs232.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 

0 connection(s) routed; 536 unrouted.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 2 secs 
Starting iterative routing. 
Routing active signals.
.....
End of iteration 1 
536 successful; 0 unrouted; (0) REAL time: 2 secs 
Constraints are met. 
Total REAL time: 2 secs 
Total CPU  time: 1 secs 
End of route.  536 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 242


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.632 ns
   The Maximum Pin Delay is:                               6.782 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.979 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
         161         253          54          27          41           0

Dumping design to file rs232.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.