📄 rs232.vhd
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------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 13:12:18 12/11/2007 -- Design Name: -- Module Name: RS232 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity RS232 is Port ( send : inout std_logic; rxd : in STD_LOGIC; txd : out STD_LOGIC; lcd_e : out STD_LOGIC; lcd_rw : out STD_LOGIC; lcd_rs : out STD_LOGIC; sf_d : out STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC);end RS232;architecture Behavioral of RS232 issignal sstart : std_logic :='0';signal rstart : std_logic :='0';signal lword : std_logic_vector(3 downto 0);signal hword : std_logic_vector(3 downto 0);signal state : integer range 0 to 7 := 0;Type data is array (0 to 3, 0 to 1) of std_logic_vector(3 downto 0);constant cmd : data := (("0010","1000"),--Function set ("0000","0110"),--Entry mode set ("0000","1100"),--Display on/off ("1000","0000")--Set DDram address );signal index : integer range 0 to 4 :=0;signal count2 : integer range 0 to 10 :=0;signal count1 : integer range 0 to 10 :=0;signal count0 : integer range 0 to 750000 := 0;signal count3 : integer range 0 to 50000 :=0;signal sflag : std_logic := '0';signal flag : integer range 0 to 15 := 0;signal a1,a2,a3,j,k: std_logic;signal fclk : std_logic :='0';signal srst : std_logic;beginprocess(clk)beginif rising_edge(clk) then if(state = 0) then --initializtion if(flag = 0) then if count0 = 750000 then flag <= 1; sf_d <= "0011"; lcd_e <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 1 then if count0 = 12 then flag <= 2; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 2 then if count0 = 205000 then flag <= 3; sf_d <= "0011"; lcd_e <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 3 then if count0 = 12 then flag <= 4; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 4 then if count0 = 5000 then flag <= 5; sf_d <= "0011"; lcd_e <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 5 then if count0 = 12 then flag <= 6; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 6 then if count0 = 2000 then flag <= 7; sf_d <= "0010"; lcd_e <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 7 then if count0 = 12 then flag <= 8; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; else if count0 = 2000 then flag <= 0; count0 <= 0; state <= 1; lcd_rs <= '0'; lcd_rw <= '0'; sf_d <= cmd(index,0);--the high 4bits else count0 <= count0+1; end if; end if;----------------------------------------------------------------------- elsif state = 1 then --send command if flag = 0 then --delay 40ns if count0 = 2 then flag <= 1; count0 <= 0; lcd_e <= '1'; else count0 <= count0+1; end if; elsif flag = 1 then --delay 230ns if count0 = 12 then flag <= 2; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 2 then --delay 20ns if count0 = 1 then if sflag = '0' then --the word is not finished flag <= 3; else flag <= 4; end if; lcd_rw <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 3 then --delay 1us,low 4bits if count0 = 50 then sflag <= '1'; flag <= 0; lcd_rw <= '0'; count0 <= 0; sf_d <= cmd(index,1); index <= index+1; else count0 <= count0+1; end if; elsif flag = 4 then --delay 40us, the word is finished if count0 = 2000 then sflag <= '0'; flag <= 0; lcd_rw <= '0'; count0 <= 0; if index = 4 then lcd_rs <= '1'; state <= 2; else sf_d <= cmd(index,0); end if; else count0 <= count0+1; end if; end if;------------------------------------------------------------------------- elsif state = 2 then --waiting if (rxd = '0' or rstart = '1') then --receive data start bit if count1 = 0 then rstart <= '1'; state <= 3; elsif count1=10 then --transfer finished no specific bit sf_d <= hword; count1 <= 0; rstart <= '0'; state <= 4; elsif (count1>0 and count1<5) then--low 4bits lword(count1-1) <= rxd; state <= 3; elsif (count1>4 and count1<9) then --high 4bits hword(count1-5) <= rxd; state <= 3; else state <= 3; end if; end if; if srst ='1' then sstart <= '1'; end if;
if (sstart = '1' and srst = '1') then if count2 = 0 then txd <= '0'; state <= 3; elsif count2 = 10 then count2 <= 0; sstart <= '0'; elsif count2 = 9 then txd <= '1'; state <= 3; elsif (count2>0 and count2<5) then--low 4bits txd <= lword(count2-1); state <= 3; elsif (count2>4 and count2<9) then --high 4bits txd <= hword(count2-5); state <= 3; else state <= 3; end if;
end if;------------------------------------------------------------------------- elsif state = 3 then --delay 5210 cycles if count0 = 5210 then count1 <= count1+1; state <= 2; count0 <= 0; else count0 <= count0+1; end if;--------------------------------------------------------------------------- elsif state = 4 then --send characters if flag = 0 then --delay 40ns if count0 = 2 then flag <= 1; count0 <= 0; lcd_e <= '1'; else count0 <= count0+1; end if; elsif flag = 1 then --delay 230ns if count0 = 12 then flag <= 2; lcd_e <= '0'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 2 then --delay 20ns if count0 = 1 then if sflag = '0' then --the word is not finished flag <= 3; else flag <= 4; end if; lcd_rw <= '1'; count0 <= 0; else count0 <= count0+1; end if; elsif flag = 3 then --delay 1us,low 4bits if count0 = 50 then sflag <= '1'; flag <= 0; lcd_rw <= '0'; count0 <= 0; sf_d <= lword ; else count0 <= count0+1; end if; elsif flag = 4 then --delay 40us if count0 = 2000 then sflag <= '0'; flag <= 0; lcd_rw <= '0'; state <= 2; count0 <= 0; else count0 <= count0+1; end if; end if; end if; if count3 = 50000 then --button filter count3 <= 0; fclk <= not fclk; else count3 <= count3+1; end if;end if;end process;process(fclk)beginif rising_edge(fclk) then a1 <= send; a2 <= a1; a3 <= a2; j <= a1 and a2 and a3; k <= not(a1 or a2 or a3); srst <= (j and not srst)or(not k and srst);end if;end process;end Behavioral;
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