3-1.txt

自动卖报机

module zuoye3_1(in,out,KAIG,clk);
input[2:0] in;
parameter in1=1fen,in_b010=2fen,in_b101=5fen;
input KAIG,clk;
output out;
reg out;
reg[2:0] state,n_state;
always @(posedge clk or posedge KAIG or state or in)
 begin
  if(KAIG) state=0;
  else state=n_state;
  case(state)
   3'b000:
       if(in<=1)begin
          n_state<=3'b001;
          out<=0; 
         end
       else if(in<=3'b010)begin
          n_state=3'b010;
          out<=0;
         end
       else if(in<=3'b101)begin
          n_state<=0;
          out<=1;
         end
       else begin
         n_state=0;
         out=0;
         end
    3'b001:
       if(in<=1)begin
          n_state<=3'b010;
          out<=0;
         end
        else if(in<=3'b010)begin
          n_state<=3'b011;
          out<=0;
         end
        else if(in<=3'b101)begin
          n_state<=0;
          out<=1;
         end
        else begin
          n_state=0;
          out=0;
         end
     3'b010:
       if(in<=1)begin
          n_state<=3'b011;
          out<=0;
         end
       else if(in<=3'b010)begin
          n_state<=3'b100;
          out<=0;
          end
       else if(in<=3'b101)begin
          n_state<=0;
          out<=1;
          end
       else begin
          n_state=0;
          out=0;
         end
     3'b011:
       if(in<=1)begin
          n_state<=3'b100;
          out<=0;
          end
       else if(in<=3'b010)begin
          n_state<=0;
          out<=1;
          end
       else if(in<=3'b101)begin
          n_state<=0;
          out<=1;
          end
       else begin
          n_state=0;
          out=0;
         end
     3'b100:
       if(in<=1)begin
          n_state<=0;
          out<=1;
         end
       else if(in<=3'b010)begin
          n_state<=0;
          out<=1;
          end
       else if(in<=3'b101)begin
          n_state<=0;
          out<=1;
          end
       else begin
          n_state=0;
          out=0;
         end
  endcase
 end
endmodule

module test_zuoye3_1;
reg[2:0] in;
reg clk,KAIG;
//reg[2:0]state,n_state;
wire[2:0]state,n_state;
wire out;
zuoye3_1 open(in,out,KAIG,clk);
 initial begin
  in=0;
  clk=0;
  KAIG=1;
  #50 KAIG=0;
  #40 in=3'b001;
  #40 in=3'b001;
  #40 in=3'b101;
  #40 in=3'b011;
  #40 in=3'b010;
  #40 in=3'b011;
  #40 in=3'b010;
  #40 in=3'b101;
  #40 in=3'b010;
  #40 in=3'b001;
  #40 in=3'b001;
  #40 in=3'b001;
  #40 in=3'b001;
  #40 in=3'b101;
  #40 in=3'b000;
  #40 in=3'b001;
  #40 in=3'b010;
  #40 in=3'b001;
  #40 in=3'b010;
  #40 in=3'b010;
  #40 in=3'b010;
  #40 in=3'b101;
  #40 in=3'b100;
  #40 in=3'b101;
  #40 in=3'b000;
  #40 in=3'b001;
  #40 in=3'b010;
  #40 in=3'b010;
  #40 in=3'b001;
  #40 in=3'b001;
  #40 in=3'b101;
 end
always #30 clk=~clk;
endmodule