fir.cr.mti

fpga功能实现有限字长响应FIR 用verilog编写

E:/fpga/enter_x.v {1 {vlog -work work E:/fpga/enter_x.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module enter_x

Top level modules:
	enter_x

} {} {}} E:/homework/fpga/booth_tp.v {1 {vlog -work work E:/homework/fpga/booth_tp.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module booth_tp

Top level modules:
	booth_tp

} {} {}} E:/homework/fpga/booth.v {1 {vlog -work work E:/homework/fpga/booth.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module booth

Top level modules:
	booth

} {} {}} E:/fpga/booth_tp.v {1 {vlog -work work E:/fpga/booth_tp.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module booth_tp

Top level modules:
	booth_tp

} {} {}} E:/fpga/CSA4.v {1 {vlog -work work E:/fpga/CSA4.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module CSA4

Top level modules:
	CSA4

} {} {}} E:/fpga/booth.v {1 {vlog -work work E:/fpga/booth.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module booth

Top level modules:
	booth

} {} {}} E:/fpga/full_add1.v {1 {vlog -work work E:/fpga/full_add1.v
Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb  2 2005
-- Compiling module full_add1

Top level modules:
	full_add1

} {} {}}