int_to_vector_suo.vhd

来自「整型到字符型的转换」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;

entity int_to_vector_suo is
    port(input:in integer range 0 to 255;
          q:out std_logic_vector(7 downto 0));
end int_to_vector_suo;

architecture behave of int_to_vector_suo is
begin
   process(input)
   variable tmp,t:integer;
   begin
	t:=input;
     for i in 0 to 7 loop
       tmp:=t/2;
       if((t rem 2)=1)then
			q(i)<='1';
		else
			q(i)<='0';
		end if;
       t:=tmp;
     end loop;
   end process;
end behave;