int_to_vector_suo.vo

整型到字符型的转换

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "10/29/2007 12:09:50"

// 
// Device: Altera EP2S15F484C3 Package FBGA484
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module int_to_vector_suo (
	\input ,
	q);
input 	[7:0] \input ;
output 	[7:0] q;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("int_to_vector_suo_v.sdo");
// synopsys translate_on

wire \input[0]~combout ;
wire \input[1]~combout ;
wire \input[2]~combout ;
wire \input[3]~combout ;
wire \input[4]~combout ;
wire \input[5]~combout ;
wire \input[6]~combout ;
wire \input[7]~combout ;


// atom is at PIN_U9
stratixii_io \input[0]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[0]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [0]));
// synopsys translate_off
// defparam \input[0]~I .ddio_mode = "none";
// defparam \input[0]~I .ddioinclk_input = "negated_inclk";
// defparam \input[0]~I .dqs_delay_buffer_mode = "none";
// defparam \input[0]~I .dqs_out_mode = "none";
// defparam \input[0]~I .inclk_input = "normal";
// defparam \input[0]~I .input_async_reset = "none";
// defparam \input[0]~I .input_power_up = "low";
// defparam \input[0]~I .input_register_mode = "none";
// defparam \input[0]~I .input_sync_reset = "none";
// defparam \input[0]~I .oe_async_reset = "none";
// defparam \input[0]~I .oe_power_up = "low";
// defparam \input[0]~I .oe_register_mode = "none";
// defparam \input[0]~I .oe_sync_reset = "none";
// defparam \input[0]~I .operation_mode = "input";
// defparam \input[0]~I .output_async_reset = "none";
// defparam \input[0]~I .output_power_up = "low";
// defparam \input[0]~I .output_register_mode = "none";
// defparam \input[0]~I .output_sync_reset = "none";
// defparam \input[0]~I .sim_dqs_delay_increment = 0;
// defparam \input[0]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[0]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_A15
stratixii_io \input[1]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[1]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [1]));
// synopsys translate_off
// defparam \input[1]~I .ddio_mode = "none";
// defparam \input[1]~I .ddioinclk_input = "negated_inclk";
// defparam \input[1]~I .dqs_delay_buffer_mode = "none";
// defparam \input[1]~I .dqs_out_mode = "none";
// defparam \input[1]~I .inclk_input = "normal";
// defparam \input[1]~I .input_async_reset = "none";
// defparam \input[1]~I .input_power_up = "low";
// defparam \input[1]~I .input_register_mode = "none";
// defparam \input[1]~I .input_sync_reset = "none";
// defparam \input[1]~I .oe_async_reset = "none";
// defparam \input[1]~I .oe_power_up = "low";
// defparam \input[1]~I .oe_register_mode = "none";
// defparam \input[1]~I .oe_sync_reset = "none";
// defparam \input[1]~I .operation_mode = "input";
// defparam \input[1]~I .output_async_reset = "none";
// defparam \input[1]~I .output_power_up = "low";
// defparam \input[1]~I .output_register_mode = "none";
// defparam \input[1]~I .output_sync_reset = "none";
// defparam \input[1]~I .sim_dqs_delay_increment = 0;
// defparam \input[1]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_W16
stratixii_io \input[2]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[2]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [2]));
// synopsys translate_off
// defparam \input[2]~I .ddio_mode = "none";
// defparam \input[2]~I .ddioinclk_input = "negated_inclk";
// defparam \input[2]~I .dqs_delay_buffer_mode = "none";
// defparam \input[2]~I .dqs_out_mode = "none";
// defparam \input[2]~I .inclk_input = "normal";
// defparam \input[2]~I .input_async_reset = "none";
// defparam \input[2]~I .input_power_up = "low";
// defparam \input[2]~I .input_register_mode = "none";
// defparam \input[2]~I .input_sync_reset = "none";
// defparam \input[2]~I .oe_async_reset = "none";
// defparam \input[2]~I .oe_power_up = "low";
// defparam \input[2]~I .oe_register_mode = "none";
// defparam \input[2]~I .oe_sync_reset = "none";
// defparam \input[2]~I .operation_mode = "input";
// defparam \input[2]~I .output_async_reset = "none";
// defparam \input[2]~I .output_power_up = "low";
// defparam \input[2]~I .output_register_mode = "none";
// defparam \input[2]~I .output_sync_reset = "none";
// defparam \input[2]~I .sim_dqs_delay_increment = 0;
// defparam \input[2]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AB13
stratixii_io \input[3]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[3]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [3]));
// synopsys translate_off
// defparam \input[3]~I .ddio_mode = "none";
// defparam \input[3]~I .ddioinclk_input = "negated_inclk";
// defparam \input[3]~I .dqs_delay_buffer_mode = "none";
// defparam \input[3]~I .dqs_out_mode = "none";
// defparam \input[3]~I .inclk_input = "normal";
// defparam \input[3]~I .input_async_reset = "none";
// defparam \input[3]~I .input_power_up = "low";
// defparam \input[3]~I .input_register_mode = "none";
// defparam \input[3]~I .input_sync_reset = "none";
// defparam \input[3]~I .oe_async_reset = "none";
// defparam \input[3]~I .oe_power_up = "low";
// defparam \input[3]~I .oe_register_mode = "none";
// defparam \input[3]~I .oe_sync_reset = "none";
// defparam \input[3]~I .operation_mode = "input";
// defparam \input[3]~I .output_async_reset = "none";
// defparam \input[3]~I .output_power_up = "low";
// defparam \input[3]~I .output_register_mode = "none";
// defparam \input[3]~I .output_sync_reset = "none";
// defparam \input[3]~I .sim_dqs_delay_increment = 0;
// defparam \input[3]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_J5
stratixii_io \input[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[4]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [4]));
// synopsys translate_off
// defparam \input[4]~I .ddio_mode = "none";
// defparam \input[4]~I .ddioinclk_input = "negated_inclk";
// defparam \input[4]~I .dqs_delay_buffer_mode = "none";
// defparam \input[4]~I .dqs_out_mode = "none";
// defparam \input[4]~I .inclk_input = "normal";
// defparam \input[4]~I .input_async_reset = "none";
// defparam \input[4]~I .input_power_up = "low";
// defparam \input[4]~I .input_register_mode = "none";
// defparam \input[4]~I .input_sync_reset = "none";
// defparam \input[4]~I .oe_async_reset = "none";
// defparam \input[4]~I .oe_power_up = "low";
// defparam \input[4]~I .oe_register_mode = "none";
// defparam \input[4]~I .oe_sync_reset = "none";
// defparam \input[4]~I .operation_mode = "input";
// defparam \input[4]~I .output_async_reset = "none";
// defparam \input[4]~I .output_power_up = "low";
// defparam \input[4]~I .output_register_mode = "none";
// defparam \input[4]~I .output_sync_reset = "none";
// defparam \input[4]~I .sim_dqs_delay_increment = 0;
// defparam \input[4]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_U12
stratixii_io \input[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[5]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [5]));
// synopsys translate_off
// defparam \input[5]~I .ddio_mode = "none";
// defparam \input[5]~I .ddioinclk_input = "negated_inclk";
// defparam \input[5]~I .dqs_delay_buffer_mode = "none";
// defparam \input[5]~I .dqs_out_mode = "none";
// defparam \input[5]~I .inclk_input = "normal";
// defparam \input[5]~I .input_async_reset = "none";
// defparam \input[5]~I .input_power_up = "low";
// defparam \input[5]~I .input_register_mode = "none";
// defparam \input[5]~I .input_sync_reset = "none";
// defparam \input[5]~I .oe_async_reset = "none";
// defparam \input[5]~I .oe_power_up = "low";
// defparam \input[5]~I .oe_register_mode = "none";
// defparam \input[5]~I .oe_sync_reset = "none";
// defparam \input[5]~I .operation_mode = "input";
// defparam \input[5]~I .output_async_reset = "none";
// defparam \input[5]~I .output_power_up = "low";
// defparam \input[5]~I .output_register_mode = "none";
// defparam \input[5]~I .output_sync_reset = "none";
// defparam \input[5]~I .sim_dqs_delay_increment = 0;
// defparam \input[5]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_K6
stratixii_io \input[6]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[6]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(\input [6]));
// synopsys translate_off
// defparam \input[6]~I .ddio_mode = "none";
// defparam \input[6]~I .ddioinclk_input = "negated_inclk";
// defparam \input[6]~I .dqs_delay_buffer_mode = "none";
// defparam \input[6]~I .dqs_out_mode = "none";
// defparam \input[6]~I .inclk_input = "normal";
// defparam \input[6]~I .input_async_reset = "none";
// defparam \input[6]~I .input_power_up = "low";
// defparam \input[6]~I .input_register_mode = "none";
// defparam \input[6]~I .input_sync_reset = "none";
// defparam \input[6]~I .oe_async_reset = "none";
// defparam \input[6]~I .oe_power_up = "low";
// defparam \input[6]~I .oe_register_mode = "none";
// defparam \input[6]~I .oe_sync_reset = "none";
// defparam \input[6]~I .operation_mode = "input";
// defparam \input[6]~I .output_async_reset = "none";
// defparam \input[6]~I .output_power_up = "low";
// defparam \input[6]~I .output_register_mode = "none";
// defparam \input[6]~I .output_sync_reset = "none";
// defparam \input[6]~I .sim_dqs_delay_increment = 0;
// defparam \input[6]~I .sim_dqs_intrinsic_delay = 0;
// defparam \input[6]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_C9
stratixii_io \input[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.modesel(36'b000000000000000000000000000000000001),
	.combout(\input[7]~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),